André Seznec

André Seznec

Contact information

André SeznecIRISA/INRIA
Campus de Beaulieu
35042 RENNES Cedex
FRANCE

tel : +33 2 99 84 73 36
fax : +33 2 99 84 71 71

E-mail: andre.seznec@inria.fr

In a few bullets:

My past research

As a programmer I am fundamentally a sequential guy.. Therefore my past researches in computer architecture have essentially focussed on providing performance for sequential programs, mainly on a single processor. Here is a list of topics I have been active for a few years ( and still proud of the contributionsSmile)

For a synthesis of my 2011-2016  research, see DAL, Defying Amdahl’s Law

Former PhD students (most recently known professional websites)

K. Courtel (1991), N. Drach (1994), S. Hily (1997), D. Truong (co-advisor F. Bodin, 1998), E . Rohou (co-advisor F. Bodin, 1998), P. Michaud (1998), T. Lafage (2000), A. Fraboulet (2004), A. Darsch (2004),A. Djabelkhir (2005), E. Toullec(2005), O. Rochecouste (2005), C. Lauradoux (co-advisor N. Sendrier, 2007), T. Piquet ( 2008), J. Dusser ( 2010), J. Lai (2-2013), R. Vélàsquez (4-2013, co-advisor P. Michaud), B. Lesage (5-2013, co-advisor I. Puaut), N. Prémillieu (12-2013),B. Swamy (02-2015), S. Natarajan (06-2015), A. Perais (09-2015), A. Suresh (co-advisor E. Rohou,, 05-2016), S. Kalathingal (co-advisor S. Collange, 12-2016), A. Sridaran (12-2016),

Current PhD students (see their ALF page)

A. Mondelli (co-advisor P. Michaud, 10-2013, ..),  K. Kalaitzidis (12-2016, ..) , N. Charmchi (01-2017, ..)

Most significant publications

Ph.D. dissertation

  1. A.Seznec “Contribution à l’étude des multiprocesseurs fortement pipelinés” Thèse d’état, Université de Rennes I, June 1987

International journals

  1. Y.Jégou, A.Seznec, “Data Synchronized Pipeline Architecture : pipelining in multiprocessor environment” Journal of Parallel and Distributed Computing, Dec. 1986 (also Proceedings International Conference on Parallel Processing 1986 (ACM), St-Charles, Illinois Aug. 1986)
  2. A.Seznec, “A new interconnection network for SIMD computers : The Sigma network” IEEE Transactions on Computers, July 1987
  3. A. Seznec, J. Lenfant, “Interleaved Parallel Schemes”, IEEE Transactions on Parallel and Distributed Systems, Dec 1994.
  4. A. Seznec, J. Lenfant, “Odd memory systems: A new approach”, Journal of Parallel and Distributed Computing, May 1995.
  5. N. Drach, A. Gefflaut, P. Joubert, A. Seznec, “About cache associativity in low-cost shared memory multi-microprocessors”, Parallel Processing Letters, Sept. 1995 (also IRISA Report No 760)
  6. A. Seznec, “Decoupled Sectored Caches”, IEEE Transactions on Computers, Feb. 1997
  7. F. Bodin, A. Seznec, “Skewed Associativity improves performance and enhances predictability”, IEEE Transactions on Computers, May 1997
  8. E. Rohou, F. Bodin, C. Eisenbeis, A. Seznec, “Handling Global Constraints in Compiler Strategy”, International Journal of Parallel Programming, august 2000.
  9. P. Michaud, A. Seznec, S. Jourdan, “An exploration of instruction fetch requirement in out-of-order superscalar processors”, International Journal of Parallel Programming, March 2001
  10. A. Seznec, N. Sendrier, “HAVEGE: a user-level software heuristic for generating empirically strong random numbers”, 2003, to appear in the special issue on “Random number generation and highly uniform point sets” of ACM Transaction on Modeling and Computer Simulations, October 2003 , postscript (209 Kb), pdf (278 Kb)
  11. R. Dolbeau, A. Seznec, CASH: revisiting hardware sharing in single-chip parallel processor , Journal of Instruction Level Parallelism , April 2004
  12. A. Seznec , “Concurrent Support of Multiple Page Sizes on a Skewed Associative TLB”, IEEE Transactions on Computers, July 2004
  13. Julio César Hernández Castro, José María Sierra, André Seznec, Antonio Izquierdo, Arturo Ribagorda: The strict avalanche criterion randomness test. Mathematics and Computers in Simulation 68(1): 1-7 (2005)
  14. A.Seznec, “Genesis of the OGEHL predictor“, Journal of Instruction Level Parallelism , April 2005
  15. A. Seznec, R. Espasa “Conflict-free accesses to strided vectors on a banked cache”, IEEE Transactions on Computers, July 2005, the associated C program to compute conflict free slices”
  16. A. Seznec, P. Michaud, “ A case for (partially) tagged Geometric History Length Branch Prediction”, Journal of Instruction Level Parallelism , Feb. 2006, associated TAGE simulator (gzipped)
  17. Olivier Rochecouste and Gilles Pokam and André Seznec,, A Case for a Complexity-Effective, Width-Partitioned Microarchitecture. ACM Transactions on Architecture and Code Optimisation (TACO), Volume 3 , Issue 3, September 2006.
  18. A. Seznec “The L-TAGE predictor”, Journal of Instruction Level Parallelism, May 2007
  19. A. Seznec “The idealistic GTL predictor”, Journal of Instruction Level Parallelism, May 2007
  20. P.Michaud, Y. Sazeides, A. Seznec, T. Constantinou, D. Fetis, “A study of thread migration in temperature-constrained multicores“, ACM Transactions on Architecture and Code Optimization, Volume 4, Issue 2, June 2007
  21. K. De Bosschere, G. Gaydadjiev, X. Martorell, N. Navarro, M. O’Boyle, D. Pnevmatikatos, A. Ramirez, P. Sainrat, A. Seznec, P. Stenstrom, and O. Temam. High-Performance Embedded Architecture and Compilation Roadmap. In Transactions on High-Performance Embedded Architectures and Compilers. Vol 1, No 3. Dec. 2006
  22. Hans Vandierendonck, A. Seznec: Speculative return address stack management revisited. ACM Transactions on Architecture and Code Optimization 5 (3): (2008)
  23. H. Vandierendonck, A. Seznec, “Fetch Gating Control through Speculative Instruction Window Weighting“, Transaction on HiPEAC 2: 128-148 (2009)
  24. A. Seznec, “A Phase Change Memory as a Secure Main Memory”, IEEE Computer Architecture Letters, Feb 2010.
  25. Hans Vandierendonck, Andre Seznec, “Fairness Metrics for Multi-Threaded Processors,” IEEE Computer Architecture Letters, vol. 99, Feb. 2011
  26. H. Vandierendonck, A. Seznec, “Managing SMT Resource Usage through Speculative Instruction Window Weighting“, ACM Transactions on Architecture and Code Optimization , October 2011.
  27. N. Prémillieu, A. Seznec, “SYRANT: SYmmetric resource allocation on not-taken and taken path“, ACM Transactions on Architecture and Code Optimization , Jan 2012.
  28. R. A. Velasquez, P. Michaud, and A. Seznec, ”BADCO : Behavioral Application-Dependent superscalar COre model”,International Journal of Parallel Programming, Feb 2015
  29. N. Prémillieu, A. Seznec, “Efficient Out-of-Order Execution of Guarded ISAs, ACM Transactions on Architecture and Code Optimization , Dec 2014.
  30. Arjun Suresh, Bharath Narasimha Swamy, Erven Rohou, André Seznec, “Intercepting Functions for Memoization: A Case Study Using Transcendental Functions”, ACM Transactions on Architecture and Code Optimization , June 2015
  31. Pierre Michaud, Andrea Mondelli, André Seznec Revisiting Clustered Microarchitecture for Future Superscalar Cores: A Case for Wide Issue Clusters ACM Transactions on Architecture and Code Optimization (TACO) , ACM, 2015, 13 (3), pp.22.
  32. Arthur Perais, André Seznec EOLE: Toward a Practical Implementation of Value Prediction IEEE Micro, Institute of Electrical and Electronics Engineers, 2015, Micro’s Top Picks from the 2014 Computer Architecture Conferences, 35 (3), pp.114 – 124. <https://www.computer.org/web/computingnow/micro>.
  33. Arthur Perais, André Seznec EOLE: Combining Static and Dynamic Scheduling through Value Prediction to Reduce Complexity and Increase Performance TOCS – ACM Transactions on Computer Systems, ACM, 2016,
  34. André Seznec, Joshua San Miguel, Jorge Albericio, Practical Multidimensional Branch Prediction IEEE Micro, 2016,Micro’s Top Picks from the 2015 Computer Architecture Conferences,
  35. Somayeh Sardashti, A. Seznec, David A. Wood. Yet Another Compressed Cache: a Low Cost Yet Effective Compressed Cache. ACM Transactions on Architecture and Code Optimization, Association for Computing Machinery, 2016, pp.25. <http://taco.acm.org/>. <hal-01354248>
  36. Arthur Perais, André Seznec. Storage-Free Memory Dependency Prediction. IEEE Computer Architecture Letters, Institute of Electrical and Electronics Engineers, 2016, pp.1 – 4. <10.1109/LCA.2016.2628379>. <hal-01396985>

Book chapters

  1. T. Lafage, A. Seznec, “Choosing Representative Slices of Program execution for Microarchitecture Simulations: A Preliminary Application to the Data Stream”, Workload Characterization of Emerging Applications, Kluwer Academic Publishers, also Workshop on Workload Characterization (WWC 2000), september 2000.
  2. A. Seznec : ”Branch Predictors”. Encyclopedia of Parallel Computing 2011 : 176-182

Proceedings Editor

  1. Paul Feautrier, James R. Goodman, André Seznec:
    Proceedings of the 18th Annual International Conference on Supercomputing, ICS 2004, Saint Malo, France, June 26 – July 01, 2004.ACM2004, ISBN 1-58113-839-3
  2. André Seznec, Joel S. Emer, Michael F. P. O’Boyle, Margaret Martonosi, Theo Ungerer: High Performance Embedded Architectures and Compilers, Fourth International Conference, HiPEAC 2009, Paphos, Cyprus, January 25-28, 2009. Proceedings Springer 2009
  3. André Seznec, Uri C. Weiser, Ronny Ronen:
    37th International Symposium on Computer Architecture (ISCA 2010), June 19-23, 2010, Saint-Malo, France. ACM 2010, ISBN 978-1-4503-0053-7
  4. Christian Fensch, Michael F. P. O’Boyle, André Seznec, François Bodin:
    Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques, Edinburgh, United Kingdom, September 7-11, 2013.IEEE Computer Society 2013, ISBN 978-1-4799-1018-2

Major conferences

International Symposium on Computer Architecture (ISCA)

  1. A.Seznec, “An efficient routing control unit for the Sigma network” Proceedings of the 13th International Symposium on Computer Architecture (IEEE-ACM) Tokyo, June 1986,
  2. A.Seznec, Y.Jégou “Synchronizing processors through memory requests in a tightly coupled multiprocessor” Proceedings of the 15th International Symposium on Computer Architecture (IEEE-ACM), Honolulu, June 1988
  3. A.Seznec, J. Lenfant “Interleaved Parallel Schemes: improving memory throughput on vector supercomputers” Proceeding of the 19th International Symposium on Computer Architecture (IEEE-ACM), Queensland, May 1992
  4. A. Seznec, “A case for two-way skewed-associative cache”, Proceedings of the 20th International Symposium on Computer Architecture(IEEE-ACM), San Diego, May 1993
  5. A. Seznec, J. Lenfant, “Odd Memory Systems may be quite interesting”, Proceedings of the 20th International Symposium On Computer Architecture (IEEE-ACM), San Diego, May 1993
  6. A. Seznec, “Decoupled sectored caches: reconciliating low tag volume and low miss ratio”, Proceedings of the 21th International Symposium on Computer Architecture(IEEE-ACM), Chicago, april 1994
  7. F. Bodin, A. Seznec, “Skewed-associativity enhances performance predictability“,Proceedings of the 22th International Symposium on Computer Architecture (IEEE-ACM), Santa-Margharita, june 1995 (also IRISA Report No 909 )
  8. A. Seznec, “Don’t use the page number, but a pointer to it”, Proceedings of the 23rd International Symposium on Computer Architecture (IEEE-ACM), Philadelphie, may 1996.
  9. P.Michaud, A. Seznec, R. Uhlig, “ Trading conflict and capacity aliasing in conditional branch predictors ”, Proceedings of the 24th International Symposium on Computer Architecture (IEEE-ACM), Denver, june 1997
  10. A. Seznec, S. Felix, V. Krishnan, Y. Sazeides , “Design trade-offs on the EV8 branch predictor“, Slides (Powerpoint) , Proceedings of the 29th International Symposium on Computer Architecture (IEEE-ACM), Anchorage, may 2002
  11. R. Espasa, F. Ardanaz, J. Emer, S. Felix, J. Gago, R. Gramunt, I. Hernandez, T. Juan, G. Lowney, M. Mattina, A. Seznec, “Tarantula: A vector Extension to the Alpha Architecture”, Proceedings of the 29th International Symposium on Computer Architecture (IEEE-ACM), Anchorage, may 2002
  12. A. Seznec, A. Fraboulet, “Effective ahead pipelining of instruction block address generation”, Proceedings of the 30th International Symposium on Computer Architecture (IEEE-ACM), San Diego, june 2003
  13. A. Seznec, “Analysis of the OGEHL predictor”, Proceedings of the 32th International Symposium on Computer Architecture (IEEE-ACM), Madison, june 2005
  14. A. Perais and A. Seznec. EOLE: Paving the Way for an Effective Implementation of Value Prediction. In Proc. of the 41th International Symposium on Computer Architecture (ISCA41), 2014. Slides, Fast Forward Slides.
  15. A. Perais, A. Seznec, P. Michaud, A. Sembrant, E. Hagersten. “Cost-Effective Speculative Scheduling in High Performance Processors”, Proceedings of the 42nd International Symposium on Computer Architecture (ISCA42), June 2015

International Symposium on Microarchitecture (Micro)

  1. A.Seznec, K.Courtel “Controlling and sequencing an heavily pipelined floating-point operator”, Proceedings of the 25th IEEE International Symposium on Microarchitecture (MICRO 25), Portland, Dec. 1992
  2. N. Drach, A. Seznec, “MIDEE: Smoothing Branch and Instruction Cache Miss Penalties on Deep Pipelines”, Proceedings of the 26th International Symposium on Microarchitecture (ACM-IEEE), Austin, Dec.993 (also RR INRIA 2038)
  3. A. Seznec, E. Toullec, O. Rochecouste “Register Write Specialization Register Read Specialization: A Path to Complexity Effective of Wide Issue Superscalar Processors”, Slides (Powerpoint) , Proceedings of the 35th International Symposium on Microarchitecture (ACM-IEEE), Istambul, Nov. 2002
  4. A. Seznec, “A new case for the TAGE branch predictor“, Proceedings of the 44th International Symposium on Microarchitecture (ACM-IEEE), Porto Allegre, Dec. 2011.
  5. S. Sardashti, A. Seznec and D.A. Wood Skewed Compressed Caches, The 47th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-47), Dec.2014. Slides
  6. Andreas Sembrant, Trevor Carlson, Erik Hagersten, David Black-Shaffer, Arthur Perais, André Seznec, Pierre Michaud Long Term Parking (LTP): Criticality-aware Resource Allocation in OOO Processors International Symposium on Microarchitecture, Micro 2015, Dec 2015, Honolulu, United States. ACM, pp.11, 2015,
  7. André Seznec, Joshua San Miguel, Jorge Albericio, The Inner Most Loop Iteration counter: a new dimension in branch history , 48th International Symposium On Microarchitecture, Dec 2015, Honolulu, United States.
  8. Arthur Perais, Fernando A. Endo, André Seznec. Register Sharing for Equality Prediction. 49th International Symposium on Microarchitecture, Oct 2016, Taipei, Taiwan. 2016, <hal-01354267>
  9. Biswabandan Panda, André Seznec. Dictionary Sharing: An Efficient Cache Compression Scheme for Compressed Caches. 49th Annual IEEE/ACM International Symposium on Microarchitecture, 2016, Oct 2016, Taipei, Taiwan. <hal-01354246>

International Symposium on High Performance Computer Architecture (HPCA)

  1. A. Seznec,”DASC cache“, Proceedings of the First High Performance Computer Architecture(IEEE), Raleigh (USA), January 1995 (also RR INRIA 2082)
  2. S. Hily, A. Seznec “ Out-Of-Order Execution May Not Be Cost-Effective on Processors Featuring Simultaneous Multithreading”,Proceedings of the Fiftht High Performance Computer Architecture(IEEE), Orlando (USA), January 1999, longer version available as IRISA Report No 1179, March 1998
  3. P. Michaud, A. Seznec, “Data-flow prescheduling for large instruction windows in out-of-order processors”,Proceedings of the 7th international Conference on High Performance Computer Architecture, January 2001
  4. A. Seznec “Storage Free Confidence Estimation for the TAGE branch predictor“, Proceedings of the 17th international Conference on High Performance Computer Architecture, Feb 2011
  5. M. K. Qureshi, A.Seznec, L. A. Lastras, , M. M. Franceschini “Practical and Secure PCM Systems by Online Detection of Malicious Write Streams ” , Proceedings of the 17th international Conference on High Performance Computer Architecture, Feb 2011
  6. A. Perais and A. Seznec. Practical Data Value Speculation for Future High-end Processors. In Proc. of the 20th International Symposium on High Performance Computer Architecture (HPCA20), 2014. Slides.
  7. M. Papadopoulou, X. Tong, A. Seznec, A. Moshovos, Prediction-Based Superpage-Friendly TLB Designs”, In Proc. of the 20th International Symposium on High Performance Computer Architecture (HPCA21), Feb. 2015
  8. A. Perais and A. Seznec. BeBoP: A Cost Effective Predictor Infrastructure for Superscalar Value Prediction. In Proc. of the 21th International Symposium on High Performance Computer Architecture (HPCA21), Feb. 2015.
  9. Arthur Perais, André Seznec Cost Effective Physical Register Sharing International Symposium on High Performance Computer Architecture, Mar 2016, Barcelona, Spain.

Architectural Support on Programming Languages and Operating Systems (ASPLOS)

  1. A. Seznec, S.Jourdan, P. Sainrat, P. Michaud, “ Multiple-Block Ahead Branch Predictors”, Proceedings of the 7th conference on Architectural Support for Programming Languges and Operating Systems, Boston, October 1996

International Conference on Parallel Archictectures and Compiler Techniques (PACT)

  1. N. Drach, A. Seznec, D. Windheiser,“Direct-mapped versus set-associative pipelined caches”, Proceedings of PACT’ 95 (Parallel Architectures and Compiler Techniques), Chypre, June 1995 (also IRISA Report No 803)
  2. S. Hily, A. Seznec “ Branch prediction and simultaneous multithreading”, Proceedings of PACT’ 96(Parallel Architectures and Compiler Techniques), Boston, October 1996
  3. D. Truong, F. Bodin, A. Seznec, “ Improving Cache Behavior of Dynamically Allocated Data Structures” Proceedings of PACT’98, Paris , october 1998
  4. P. Michaud, A. Seznec, S. Jourdan, “Exploring Instruction-Fetch Bandwidth requirement in Wide-Issue Superscalar Processors”, International Conference on Parallel Architectures and Compilation Techniques, Newport Beach, October 12-16, 1999.

International Symposium on Code Generation and Optimization (CGO)

  1. Junjie Lai and André Seznec. Performance upperbound analysis and optimization of sgemm on fermi and kepler gpus. In International Symposium on Code Generation and Optimization, 2013
  2. Erven Rohou, Bharath Narasimha Swamy, André Seznec. Branch Prediction and the Performance of Interpreters – Don’t Trust Folklore, International Symposium on Code Generation and Optimization, Feb 2015

International Conference on Supercomputing (ICS)

  1. A.Seznec, Y.Jégou “Towards a large number of processors in a tightly coupled multiprocessor using no cache” Proceedings of the International Conference on Supercomputing (ACM), Saint-Malo, July 1988
  2. Y.Jégou, A.Seznec, “An Asynchronous Buffering Network for Tightly Coupled Multiprocessors” Proceedings of the International Conference on Supercomputing (ACM), Heraklion, June 1989
  3. Julien Dusser, Thomas Piquet, André Seznec, “Zero content augmented cache” Proceedings of the International Conference on Supercomputing, June 2009

International Conference on Parallel Processing (ICPP)

  1. Y.Jégou, A.Seznec, “Data Synchronized Pipeline Architecture : pipelining in multiprocessor environment” , Proceedings International Conference on Parallel Processing 1986 (ACM), St-Charles, Illinois Aug. 1986
  2. A.Seznec, Y.Jégou “Optimizing memory throughput in a tightly coupled multiprocessor” Proceedings International Conference on Parallel Processing 1987 (ACM), St-Charles, Illinois, Aug. 1987
  3. N. Drach, A. Seznec, “Semi-Unified Caches”, Proceedings of the International Conference on Parallel Processing, St Charles, Illinois, Aug. 1993

Other international conferences

  1. Y.Jégou, A.Seznec “The DSPA multipipeline” Working Conference on Parallel Processing (IFIP), Pise, April 1988
  2. A. Seznec, F. Bodin, “Skewed-associative caches”, Proceedings of PARLE’ 93, Munich, June 1993
  3. A. Seznec, “About set and skewed associativity on second level caches”, Proceedings of the International Conference on Computer Design, Boston, October 1993
  4. Bas Aarts, Michel Barreteau, François Bodin, Peter Brinkhaus, Zbigniew Chamski, Henri-Pierre Charles, Christine Eisenbeis, John R. Gurd, Jan Hoogerbrugge, Ping Hu, William Jalby, Peter M.W. Knijnenburg, Michael F.P. O’Boyle, Erven Rohou, Rizos Sakellariou, Henk Schepers, André Seznec, Elena A. Stöhr, Marco Verhoeven, Harry A.G. Wijshoff “OCEANS: Optimizing Compilers for Embedded HPC Applications” Proceedings of Europar’97 – August 1997 Lecture Notes in Computer Science 1300 – Springer Verlag
  5. Michel Barreteau, François Bodin, Peter Brinkhaus, Zbigniew Chamski, Henri-Pierre Charles, Christine Eisenbeis, John R. Gurd,Jan Hoogerbrugge, Ping Hu, William Jalby, Peter M. W. Knijnenburg, Michael F. P. O’Boyle, Erven Rohou, Rizos Sakellariou, André Seznec, Elena Stöhr, Menno Treffers, Harry A. G. Wijshoff: OCEANS: Optimising Compilers for Embedded Applications. Euro-Par 1998: 1123-1130
  6. Michel Barreteau, François Bodin, Zbigniew Chamski, Henri-Pierre Charles, Christine Eisenbeis, John R. Gurd, Jan Hoogerbrugge,Ping Hu, William Jalby, Toru Kisuki, Peter M. W. Knijnenburg, Paul van der Mark, Andy Nisbet, Michael F. P. O’Boyle, Erven Rohou, André Seznec, Elena Stöhr, Menno Treffers, Harry A. G. Wijshoff: OCEANS – Optimising Compilers for Embedded Applications. Euro-Par 1999: 1171-1175
  7. Thierry Lafage, André Seznec, Erven Rohou, François Bodin: Code Cloning Tracing: A “Pay per Trace” Approach. Euro-Par 1999: 1265-1268
  8. Thierry Lafage, André Seznec: Combining Light Static Code Annotation and Instruction-Set Emulation for Flexible and Efficient On-the-Fly Simulation (Research Note). Euro-Par 2000: 178-182
  9. Kun Luo, Manoj Franklin, Shubhendu S. Mukherjee, André Seznec: Boosting SMT Performance by Speculation Control. IPDPS 2001: 2
  10. Julio César Hernández Castro, José María Sierra, André Seznec: The SAC Test: A New Randomness Test, with Some Applications to PRNG Analysis. ICCSA (1) 2004: 960-967
  11. Amaury Darsch, André Seznec: IATO: A Flexible EPIC Simulation Environment. SBAC-PAD 2004: 58-65
  12. G. Pokam, O. Rochecouste, A. Seznec, F. Bodin “Speculative Software Management of Datapath-width for Energy Optimization”, LCTES’04, June 2004
  13. H. Vandierendonck, A. Seznec, Fetch Gating Control through Speculative Instruction Window Weighting, High Performance Embedded Architectures and Compilers. 2007. pp. 120-135
  14. Thomas Piquet, Olivier Rochecouste and André Seznec, Exploiting Single-Usage for Effective Memory Management ACSAC, Seoul, August 2007.
  15. Alin Suciu, Tudor Carean A. Seznec, “Parallel HAVEGE”, 8th International Conference on Parallel Processing and Applied Mathematics, Wroclaw, September 2009
  16. P. Michaud, Y. Sazeides, A. Seznec, “Proposition for a sequential accelerator in future general-purpose manycore processors and the problem of migration-induced cache misses“, ACM International Conference on Computing Frontiers, May 2010.
  17. J.Dusser, A.Seznec “Decoupled Zero-Compressed Memory”, Proceedings of the HiPEAC conference, January 2011
  18. R. A. Velasquez, P. Michaud, and A. Seznec, ”BADCO : Behavioral Application-Dependent superscalar COre model”, Proceedings of the 12th International Conference on Embedded Computer Systems : Architectures, Modeling, and Simulation (SAMOS), 2012.
  19. B. Lesage, I. Puaut, A. Seznec ”Partitioned REal-TIme shared cache for mixed-criticality real-time systems”, Proceedings of 20th Real-Time and Network Systems, Pont-a-Mousson, Nov 2012
  20. R.A. Velasquez, P. Michaud, A. Seznec,. Selecting Benchmark Combinations for the Evaluation of Multicore Throughput. In International Symposium on Performance Analysis of Systems and Software. April 2013
  21. B. Swamy, A. Ketterlin, A. Seznec, Hardware/Software helper thread prefetching on Heterogeneous Many Cores, SBAC-PAD 2014, October 2014
  22. S.Natarajan, B. Swamy and A.Seznec, An Empirical High level performance model for future many-cores” , ACM International Conference on Computing Frontiers 2015, May 2015
  23. Aswinkumar Sridharan, André Seznec Discrete Cache Insertion Policies for Shared Last Level Cache Management on Large Multicores 30th IEEE International Parallel & Distributed Processing Symposium, May 2016, Chicago, United States
  24. Sajith Kalathingal, Sylvain Collange, Bharath Narasimha Swamy, André Seznec. Dynamic Inter-Thread Vectorization Architecture: extracting DLP from TLP. International Symposium on Computer Architecture and High-Performance Computing (SBAC-PAD), Oct 2016, Los Angeles, United States. <hal-01356202>
  25. Arjun Suresh, Erven Rohou, André Seznec.   Compile-Time Function Memoization  26th International Conference on Compiler Construction, Feb 2017, Austin, United States

Some workshops and newsletter papers.

  1. N. Drach, A. Seznec,: Semi-Unified Caches: Increasing Associativity of On-Chip Caches, IEEE TCCA Newsletter, 1993
  2. A.Seznec, F. Lloansi, “About effective miss penalty on out-of-order microprocessor”, IRISA Report No 970 November 1995 (a slightly modified version appears as: A. Seznec, F. Lloansi “Performance impact of the L2 contention on out-of-order execution superscalar processors”, IEEE TCCA NEWSLETTER, March 1997)
  3. D. Truong, F. Bodin, A. Seznec “Accurate Data Layout May Boost Cache Performance, in Workshop on interaction between compilers and computer architecture Feb 1, 1997 San Antonio, and in IEEE TCCA NEWSLETTER june 1997
  4. E. Rohou, F. Bodin, A. Seznec et. al, ”SALTO : System for Assembly-Language Transformation and Optimization”, PI IRISA 1032 (129 Kb) July 1996, also Sixth Workshop on Compilers for Parallel Computers – December 1996
  5. S. Hily, A. Seznec “ Standard Memory Hierarchy Does Not Fit Simultaneous Multithreading, Proceedings of MTEAC’98 Workshop, Feb. 1998, a longer version is available as Contention on 2nd Level Cache May Limit The Effectiveness of Simultaneous Multithreading, 22 pages, IRISA Report No 1086, Feb. 1997
  6. François Bodin, Zbigniew Chamski, Christine Eisenbeis, Sylvain Lelait, Erven Rohou, Antoine Sawaya, André Seznec, and Jian Wang. Towards a retargetable framework for software pipelining. In Proceedings of the 7th International Workshop on Compilers for Parallel Computers (CPC’98), pages 90-99, Linköping, Sweden, June 1998.
  7. F.Bodin, Z. Chamski, C. Eisenbeis, E. Rohou, A. Seznec GCDS: A Compiler Strategy for Trading Code Size Against Performance in Embedded Applications , 3rd Intl. Workshop on Code Generation for Embedded Processors, Witten – Germany, March 1998.
  8. A. Djabelkhir, A. Seznec, “Characterization of embedded applications for decoupled processor architecture”, Workshop on Workload Characterization (WWC 2003), october 2003
  9. T. Constantinou, Y. Sazeides, P. Michaud, D. Fetis, A. Seznec, “Performance Implications of Single Thread Migration on a Chip Multi-Core“, ACM SIGARCH Computer Architecture News, volume 33, issue 4, November 2005.
  10. A. Seznec “Towards Phase Change Memory as a Secure Main Memory“, WEST10 workshop, in conjunction with HPCA 2010, Jan. 2010
  11. J. Lai, A. Seznec, ”Break down GPU execution time with an analytical method”, Proceedings of the 2012 Workshop on Rapid Simulation and Performance Evaluation : Methods and Tools , RAPIDO’12, Jan. 2012
  12. K. Kuroyanagi, A. Seznec, ”Service Value Aware Memory Scheduler by Estimating Request Weight and Using per-Thread Traffic Lights ”, JWAC-3 : Memory Scheduling Championship , June 2012
  13. S. Natarajan, B.Swamy and A.Seznec, “Impact of serial scaling of multi-threaded programs in many-core era“, WAMCA 2014, October 2014
  14. S. Natarajan and A. Seznec, “Sequential and Parallel Code Sections are Different: they may require different Processors”, Proceedings of the 6th Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures PARMA-DITAM ’15
  15. A. Seznec “Bank-interleaved cache or memory indexing does not require euclidean division”, WDDD 15, June 2015

My Championship Branch Prediction Record

  1. A. Seznec, The O-GEHL Branch Predictor CBP-1, December 2004, 2nd, Best Practice Award
  2. A. Seznec “Looking for limits in branch prediction with the GTL predictor”, ppt presentation, CBP-2, December 2006, Champion unlimited size conditional branch predictor
  3. A. Seznec “A 256 Kbits L-TAGE predictor”, ppt presentation, CBP-2, December 2006, Champion 256Kbits conditional branch predictor
  4. A. Seznec, ”A 64 Kbytes ISL-TAGE branch predictor”, slides, JWAC-2 : Championship Branch Prediction, june 2011, Champion conditional branch predictor
  5. A. Seznec, ”A 64-Kbytes ITTAGE indirect branch predictor”, slides, JWAC-2 : Championship Branch Prediction, june 2011, Champion indirect branch predictor
  6. A.Seznec, TAGE-SC-L branch predictors”, slides JWAC-4: Championship Branch Prediction, june 2014, Champion 32Kbits and 256 Kbits conditional branch predictor
  7. P. Michaud, A. Seznec , “Pushing the Branch Predictability Limits with the Multi-poTAGE+SC Predictor”, slides Championship Branch Prediction, June 2014, Champion unlimited size conditional branch predictor
  8. André Seznec. TAGE-SC-L Branch Predictors Again. 5th JILP Workshop on Computer Architecture Competitions (JWAC-5): Championship Branch Prediction (CBP-5), Jun 2016, Seoul, South Korea. <http://www.jilp.org/cbp2016/>. <hal-01354253> Champion 32Kbits and 256 Kbits conditional branch predictor
  9. André Seznec. Exploring branch predictability limits with the MTAGE+SC predictor *. 5th JILP Workshop on Computer Architecture Competitions (JWAC-5): Championship Branch Prediction (CBP-5), Jun 2016, Seoul, South Korea. <http://www.jilp.org/cbp2016/>. <hal-01354251> Champion unlimited size conditional branch predictor

A few “interesting” research reports (I would still recommend them)

  1. A. Seznec A New Case for Skewed-Associativity”, 23 pages, IRISA Report No 1114, July 1997
  2. P. Michaud, A. Seznec, S. Jourdan, P. Sainrat Alternative Schemes for High-Bandwidth Instruction Fetching , IRISA Report No 1180, March 1998
  3. A. Seznec, P. Michaud Dealiased Hybrid Branch Predictors , IRISA Report No 1229, Feb. 1999
  4. P. Michaud, A. Seznec, A comprehensive study of dynamic global history branch prediction , IRISA Report No 1406, June 2001
  5. A. Seznec, N. Sendrier, “ HArdware Volatile Entropy Gathering and Expansion: generating unpredictable random numbers at user level“,IRISA Report, October 2002
  6. A. Seznec, Redundant History Skewed Perceptron Predictors: pushing limits on global history branch predictors , IRISA Report No 1554, sept. 2003
  7. A. Seznec, Revisiting the perceptron predictor , IRISA Report No 1620, May 2004

Technological watch on microprocessors (in french, from 1992 to 1997, all you want to know on the microarchitecture on the processors of these days)

  1. P. Laporte, A. Seznec, “ Etude comparative des microprocesseurs MIPS R3000, SPARC Version 7 et IBM Power : Architectures et Performances ”, Feb. 1992 (99 pages, postscript, 99 kO)
  2. A. Seznec, A.M. Kermarrec, T. Vauléon “ Etude Comparée des Architectures des Microprocesseurs MIPS R4000, DEC 21064 et T.I. SUPERSPARC ”, Dec. 1992 (102 pages, postscript, 223kO)
  3. A. Seznec, T. Vauléon, “ Etude comparative des architectures des microprocesseurs Intel Pentium et Power PC 601 ”, June 1994 (109 pages, postscript, 230kO)
  4. A. Seznec, Y. Mével, “ Etude des architectures des microprocesseurs IBM Power2, DEC 21164 et MIPS R8000 ”, June 1995 (128 pages, postscript, 325kO)
  5. A. Seznec, Y. Mével“ Evolutions des gammes de processeurs xxx86, MIPS Rxxx, Sparc, PowerPC et DEC Alpha ”, Dec. 1995 (110 pages, postscript, 298kO)
  6. A. Seznec, F. Lloansi“ Etude des architectures des microprocesseurs MIPS R10000, UltraSparc et PentiumPro ”, Mai 1996 (122 pages, postscript, 328 kO)
  7. A. Seznec, T. Lafage“ Evolutions des gammes de processeurs MIPS Rxxx, Dec Alpha, PowerPC, Sparc, x86 et PA-Risc ”, Juin 1997 (158 pages, postscript, 520 kO)

Patents

  1. Cache memory device
  2. Method for ensuring maximum bandwidth on accesses to strided vectors in a bank-interleaved cache
  3. Conflict free parallel read access to a bank interleaved branch predictor in a processor

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