Pipeline, registers, etc
Among the studies, I participated on core architectures (i.e. not caches, not branch predictions, not SMT, not value prediction), here are the ones that I think that they might/should influence some effective microprocessor design(s).
- P. Michaud, A. Seznec, “ Data-Flow Prescheduling for Large Instructions Windows in Out-of-Order Processors ”, 7th International Symposium on High Performance Computer Architecture, Monterrey, Mexico, January 19-24, 2001. slides
- A. Seznec, E. Toullec, O. Rochecouste “ Register Write Specialization Register Read Specialization: A Path to Complexity Effective of Wide Issue Superscalar Processors ”, Slides (Powerpoint) , Proceedings of the 35th International Symposium on Microarchitecture (ACM-IEEE), Istambul, November 2002
- P. Michaud, Y. Sazeides, A. Seznec, “Proposition for a sequential accelerator in future general-purpose manycore processors and the problem of migration-induced cache misses“, ACM International Conference on Computing Frontiers, May 2010
- A. Perais, A. Seznec, P. Michaud, A. Sembrant, E. Hagersten. “Cost-Effective Speculative Scheduling in High Performance Processors”, Proceedings of the 42nd International Symposium on Computer Architecture (ISCA42), June 2015
- Andreas Sembrant, Trevor Carlson, Erik Hagersten, David Black-Shaffer, Arthur Perais, André Seznec, Pierre Michaud Long Term Parking (LTP): Criticality-aware Resource Allocation in OOO Processors International Symposium on Microarchitecture, Micro 2015, Dec 2015, Honolulu, United States. ACM, pp.11, 2015,
- Pierre Michaud, Andrea Mondelli, André Seznec Revisiting Clustered Microarchitecture for Future Superscalar Cores: A Case for Wide Issue Clusters ACM Transactions on Architecture and Code Optimization (TACO) , ACM, 2015, 13 (3), pp.22.
- Arthur Perais, André Seznec Cost Effective Physical Register Sharing International Symposium on High Performance Computer Architecture, Mar 2016, Barcelona, Spain.
- Arthur Perais, André Seznec. Storage-Free Memory Dependency Prediction. IEEE Computer Architecture Letters, Institute of Electrical and Electronics Engineers, 2016, pp.1 – 4. <10.1109/LCA.2016.2628379>. <hal-01396985>