Parallel access to strided vectors has been an issue since the introduction of vector supercomputers. Over a period of about 20 years, I contributed on this topic for SIMD architectures (old fashioned SIMD architectures were not only considering contiguous vectors in memory), multi vector processors and finally parallel access to vectors in caches.
- A.Seznec, “An efficient routing control unit for the Sigma network” Proceedings of the 13th International Symposium on Computer Architecture (IEEE-ACM) Tokyo, June 1986,
- A.Seznec, “A new interconnection network for SIMD computers : The Sigma network” IEEE Transactions on Computers, July 1987
- A.Seznec, J. Lenfant “Interleaved Parallel Schemes: improving memory throughput on vector supercomputers” Proceeding of the 19th International Symposium on Computer Architecture (IEEE-ACM), Queensland, May 1992
- A. Seznec, J. Lenfant, “Odd Memory Systems may be quite interesting”, Proceedings of the 20th International Symposium On Computer Architecture (IEEE-ACM), San Diego, May 1993
- A. Seznec, J. Lenfant, “Interleaved Parallel Schemes”, IEEE Transactions on Parallel and Distributed Systems, Dec 1994.
- A. Seznec, J. Lenfant, “Odd memory systems: A new approach”, Journal of Parallel and Distributed Computing, May 1995.
- R. Espasa, F. Ardanaz, J. Emer, S. Felix, J. Gago, R. Gramunt, I. Hernandez, T. Juan, G. Lowney, M. Mattina, A. Seznec, “Tarantula: A vector Extension to the Alpha Architecture”, Proceedings of the 29th International Symposium on Computer Architecture (IEEE-ACM), Anchorage, may 2002
- A. Seznec, R. Espasa “Conflict-free accesses to strided vectors on a banked cache”, IEEE Transactions on Computers, July 2005,