Software for simulations
Skewed associative caches
The skewed associative cache is a new organization for multi-bank caches. Skewed-associative caches have been shown to have two major advantages over conventional set-associative caches. First, at equal associativity degrees, a skewed-associative cache typically exhibits the same hardware complexity as a set-associative cache, but exhibits lower miss ratio. This is particularly significant for BTBs and L2 caches for which a significant ratio of conflict misses occurs even on 2-way set-associative caches. Second, the behavior of skewed-associative caches is quite insensitive to the precise data placement in memory. We also showed that the skewed associative structure offers a unique opportunity to build TLBs supporting multiple page sizes.
- A. Seznec, “ A case for two-way skewed-associative cache ”, Proceedings of the 20th International Symposium on Computer Architecture(IEEE-ACM), San Diego, may 1993
- A. Seznec, F. Bodin, “Skewed-associative caches”, Proceedings of PARLE’ 93, Munich, June 1993
- A. Seznec, “About set and skewed associativity on second level caches”, Proceedings of the International Conference on Computer Design, Boston, October 1993
- F. Bodin, A. Seznec, “ Skewed-associativity improves performance and enhances predictability “, IEEE Transactions on Computers, May 1997 (A short version appears in Proceedings of the 22th International Symposium on Computer Architecture (IEEE-ACM), Santa-Margharita, June 1995)
- N. Drach, A. Gefflaut, P. Joubert, A. Seznec, “ About cache associativity in low-cost shared memory multi-microprocessors ”, Parallel Processing Letters, Sept. 1995 (also IRISA Report No 760)
- A. Seznec “ A New Case for Skewed-Associativity , 22 pages, IRISA Report No 1114, July 1997
- P. Michaud, “ A Statistical Model of Skewed Associativity ”, International Symposium on Performance Analysis of Systems and Software, Austin, March 6-8, 2003. slides
- A. Seznec, “Concurrent Support of Multiple Page Sizes on a Skewed Associative TLB”, IEEE Transactions on Computers, 2003
Minimizing tag implementation costs: the decoupled sectored cache
Most microprocessors manipulate 64-bit virtual addresses and the width of physical addresses is also now very large. As a result, the relative size of the address tags in caches is increasing. We have proposed hardware solutions to limit the implementation cost of these address tags.
Related publications:
- A. Seznec, “ Decoupled sectored caches: reconciliating low tag volume and low miss ratio ”, Proceedings of the 21th International Symposium on Computer Architecture(IEEE-ACM), Chicago, april 1994
- A. Seznec, “Decoupled sectored caches”, IEEE Transactions on Computers, Feb. 1997
- A. Seznec, “ Don’t use the page number, but a pointer to it ”, Proceedings of the 23rd International Symposium on Computer Architecture(IEEE-ACM), May 1996
Dealing with null blocks in the memory hierarchy
Many applications manipulate significant ratio of null blocks. The Zero-Content Augmented cache and the decoupled zero-compressed memory were proposed to respectively artificially increase the size of the cache and of main memory.
- Julien Dusser, Thomas Piquet, André Seznec, “Zero content augmented cache” Proceedings of the International Conference on Supercomputing, June 2009
- J.Dusser, A.Seznec “Decoupled Zero-Compressed Memory”, Proceedings of the HiPEAC conference, January 2011
When skewed caches meet compressed caches
- S. Sardashti, A. Seznec and D.A. Wood Skewed Compressed Caches, The 47th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-47), 2014. Slides
Other works on cache architecture
- N. Drach, A. Seznec, “Semi-Unified Caches”, Proceedings of the International Conference on Parallel Processing, St Charles, Illinois, August 1993 (also RR INRIA 1841)
- A. Seznec, “ DASC cache “, Proceedings of the First High Performance Computer Architecture(IEEE), Raleigh (USA), January 1995 (also RR INRIA 2082)
- A.Seznec, F. Lloansi, “ About effective miss penalty on out-of-order microprocessor ”, IRISA Report No 970 November 1995 (a slightly modified versin appears as: A. Seznec, F. Lloansi “Performance impact of the L2 contention on out-of-order execution superscalar processors”, IEEE TCCA NEWSLETTER, March 1997)
