Cache architecture research

Software for simulations

Skewed associative caches

The skewed associative cache is a new organization for multi-bank caches. Skewed-associative caches have been shown to have two major advantages over conventional set-associative caches. First, at equal associativity degrees, a skewed-associative cache typically exhibits the same hardware complexity as a set-associative cache, but exhibits lower miss ratio. This is particularly significant for BTBs and L2 caches for which a significant ratio of conflict misses occurs even on 2-way set-associative caches. Second, the behavior of skewed-associative caches is quite insensitive to the precise data placement in memory.  We also  showed that the skewed associative structure offers a unique opportunity to build TLBs supporting multiple page sizes.

Minimizing tag implementation costs: the decoupled sectored cache

Most microprocessors manipulate 64-bit virtual addresses and the width of physical addresses is also now very large. As a result, the relative size of the address tags in caches is increasing. We have proposed hardware solutions to limit the implementation cost of these address tags.

Related publications:

Dealing with null blocks in the memory hierarchy

Many applications manipulate significant ratio of null blocks. The Zero-Content Augmented cache and the decoupled zero-compressed memory were proposed to respectively artificially increase the size of the cache and of main memory.

When skewed caches meet compressed caches

  • S. Sardashti, A. Seznec and D.A. Wood Skewed Compressed Caches, The 47th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-47), 2014. Slides

Other works on cache architecture

  • N. Drach, A. Seznec, “Semi-Unified Caches”, Proceedings of the International Conference on Parallel Processing, St Charles, Illinois, August 1993 (also RR INRIA 1841)
  • A. Seznec, “ DASC cache “, Proceedings of the First High Performance Computer Architecture(IEEE), Raleigh (USA), January 1995 (also RR INRIA 2082)
  • A.Seznec, F. Lloansi, “ About effective miss penalty on out-of-order microprocessor ”, IRISA Report No 970 November 1995 (a slightly modified versin appears as: A. Seznec, F. Lloansi “Performance impact of the L2 contention on out-of-order execution superscalar processors”, IEEE TCCA NEWSLETTER, March 1997)

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