Camille presented her paper “Damas: Control-Data Isolation at Runtime through Dynamic Binary Modification” in Sep 2021 at SILM. Watch the video online!
Nassim presented his paper “WE-HML: Hybrid WCET Estimation using Machine Learning for Architectures with Caches” in Aug 2021 at RTCSA. Watch the video online!
Bahram Yarahmadi successfully defended his PhD on Thursday, July 1st, 2021. Jury members Abdoulaye GAMATIE, Senior Researcher, CNRS/LIRMM Montpellier Maria MENDEZ REAL Assistant Professor, Université de Nantes Fabrice RASTELLO, Senior Researcher, Inria Grenoble Henri-Pierre CHARLES, Senior Researcher, CEA Grenoble Olivier SENTIEYS, Professor, Université de Rennes 1 Erven Rohou, Senior Researcher, Inria Rennes Title: Static and dynamic compiler support for intermittently powered computer systems Abstract: With the advent of Internet of things (IoT), there is a need to provide energy for a massive number of smart tiny devices without using large, heavy, and high maintenance batteries. One promising way is to…
André Seznec received the award “for pioneering contributions to cache design and branch prediction” on Oct 21st, during the (virtual) MICRO conference. The IEEE CS B. Ramakrishna Rau award was established in memory of B. Ramakrishna Rau, and awarded in recognition of his distinguished career in promoting and expanding the use of innovative computer microarchitecture techniques, including his innovation in compiler technology, his leadership in academic and industrial computer architecture, and his extremely high personal and ethical standards.
Niloofar Charmchi successfully defended her PhD on Friday, July 10, 2020 at 10am. Jury members Rapporteurs : Karine HEYDEMANN Maîtresse de conférence, Sorbonne Université David DEFOUR Maître de conférence, Université de Perpignan Via Domitia Examinateurs : Florent DE DINECHIN Professeur des universités, INSA Lyon Steven DERRIEN Professeur des universités, Université Rennes 1 Directeur de thèse : André Seznec Directeur de recherches, Inria Co-dir. de thèse : Caroline Collange Chargée de recherche, Inria Title : Compressed Cache Layout Aware Prefetching Abstract: The speed gap between CPU and memory is impairing performance. Cache compression and hardware prefetching are two techniques that could…
Congratulations to Benjamin Rouxel, Stefanos Skalistis, Steven Derrien and Isabelle Puaut who received an Outstanding paper award for their paper entitled “Hiding Communication Delays in Contention-Free Execution for SPM-based Multi-Core Architectures” at the Euromicro conference on real time systems 2019 (see paper).
Automatiser le masquage des programmes contre les attaques par canal caché Même les logiciels les mieux verrouillés ont un talon d’Achille : en auscultant de près les microprocesseurs qui les exécutent, un attaquant peut mesurer certaines données physiques comme la consommation électrique ou les variations du champ magnétique.
PACAP was present at the International Cybersecurity Forum in Lille (FIC https://www.forum-fic.com/en/home.htm). We presented a demo on compiler-generated countermeasures against side-channel attacks, developed within the context of the CHIST-ERA SECODE project.