You may be interested in older projects of the team.


  • OWL: Operating Within Limits
  • ANR project
  • Granted, to be started soon.
  • Project OWL proposes a new model of computation for more frugal intelligent autonomous sensors: circadian artificial intelligence (AI). The targeted applications are in the field of  environmental monitoring, especially bioacoustic and its application to conservation ecology. This model is particularly well suited for sensors without batteries that are intermittently powered by ambient energy. The great promises of these systems is the extension of their lifetime without the need for human intervention allowing for long-term biostatistics observation missions, and a lower impact on the environment thanks to the absence of battery.
    Circadian AI is interested in observing phenomena that have a period of one day, such as the activity of birds or the pollution associated with traffic in a metropolis. It exploits the fact that this period is shared with the availability of solar energy, which is used to power the sensors. This correlation allows the systems to temporally shift the costly computations required to perform the AI functions to times when the observed phenomenon is at rest and energy is abundant.
    The project proposes two main contributions. The first is to design new algorithms for circadian AI that allow for this temporal shift in computation. The second is to provide the software and hardware infrastructure necessary to run circadian AI on intermittently powered sensors.
    The work done in the project will be based as much as possible on open source / open hardware technologies. Those built during the project (dataset, software, hardware design) will all be freely distributed.


  • AIxIA: Artificial Intelligence for Interference Analysis
  • FRAE project (Fondation de Recherche pour l’Aéronautique et l’Espace)
  • Granted, to be started soon
  • Partners: IRT Saint Exupery, Inria, Université de Rennes, IRIT
  • Demonstrating that timing contraints are met in embedded software with the required level of confidence is a challenging and costly task. One of the main issues is accounting for temporal interferences that occur between software applications sharing elements of the execution platform (e.g., cores, GPUs, interconnects, etc.). In this context, the AIxIA project aims at investigating our artificial intelligence helps in the identification of these interferences and the analysis of their effects. The project will apply artificial intelligence techniques to address three dimensions of the problem: (i) identifying the sources of interferences, (ii) quantifying and predicting their effects, and (iii) avoiding interferences.


  • Ofast3D: Optimizing Compiler for fast 3D printing
  • Inria Exploratory Action
  • 2022-2024
  • The goal of Ofast3D is to increase the production capacity of fused deposition modeling 3D printing, without requiring any modification of existing production infrastructures. Ofast3D aims to reduce printing time without impacting the print quality by optimizing the code interpreted by 3D printers during its generation by taking into account the geometry of 3D models. Ofast3D is complementary to methods aiming either at improving printers or at optimizing 3D models.


  • AoT.js: Optimizing Compilation from Higher-Order Programming to Computer Architecture
  • Inria Exploratory Action
  • 2022 to 2025
  • According to the 2022 GitHub statistics, the two most used programming languages are
    JavaScript/TypeScript (22.5 %) and Python (19 %), two dynamic languages. C/C ++ that
    used to be the dominant language, nowadays is only used in 10 % of the developments.
    However, the main characteristics of the design of the processors used to execute these
    new dynamic programs predate the programming paradigm shift. This raises three
    fundamental questions:

    1. Are the current implementations of dynamic languages able to extract the maximum
      performance of contemporary processor architectures?
    2. Are the contemporary processor architectures well suited to execute dynamic
    3. Are there any new architecture designs that could improve the execution of dynamic

    These are the long term questions we would like to address in the exploratory action
    AoT.js, combining the forces of Inria/Sophia INDES project-team and Inria/Rennes
    PACAP project-team.


  • Maplurinum: machinæ pluribus unum
  • ANR project
  • October 2021 – September 2025
  • Modern computing infrastructures are increasingly heteregenous and incorporate often specialized hardware. We have first seen the generalization of GPUs in the most powerful machines, followed a few years later by the introduction of FPGAs. More recently we have seen nascence of many other accelerators such as tensor processor units (TPUs) for DNNs or variable precision FPUs. Recent hardware manufacturing trends make it very likely that specialization will not only persist, but increase in future supercomputers. Because manually managing this heterogeneity in each application is complex and not maintainable, we propose in this project to revisit how we design both hardware and operating systems in order to better hide the heterogeneity. In summary, we propose to rethink the hardware/software boundary in order to hide the heterogeneity behind a common minimal instruction set and a unified address space.


  • NOP: Safe and Efficient Intermittent Computing for a Batteryless IoT
  • CominLabs projet
  • October 2021 to December 31, 2024
  • Intermittent computing is an emerging paradigm for batteryless IoT nodes powered by harvesting ambient energy. It intends to provide transparent support for power losses so that complex computations can be distributed over several power cycles. It aims at significantly increasing the complexity of software running on these nodes, and at reducing the volume of outgoing data. It improves the overall energy efficiency of the whole processing chain, reduces reaction latencies, and, by limiting data movements, preserves anonymity and privacy. NOP aims at improving the efficiency and usability of intermittent computing, based on consolidated theoretical foundations and a detailed understanding of energy flows within systems. For this, it brings together specialists in system architecture, energy-harvesting IoT systems, compilation, and real-time computing, to address the following scientific challenges:
    1. develop sound formal foundations for intermittent systems,
    2. develop precise predictive energy models of a whole node (including both harvesting and consumption) usable for online decision making,
    3. significantly improve the energy efficiency of run-time support for intermittency,
    4. develop techniques to provide formal guarantee through static analysis of the systems behavior (forward progress),
    5. develop a proof of concept: an intermittent system for song bird recognition, to assess
      the costs and benefits of the proposed solutions.


  • ARSENE: Architectures Sécurisées pour le Numérique Embarqué

  • France 2030, PEPR
  • August 2022 – 2027
  • ARSENE is a “PEPR Cybersécurité” project focusing on the development of sovereign solutions for hardware and software security. It aims at securing processors and peripherals such as memories or random generators. To this end, it is key to master the different levels of abstraction: hardware design, compilers, operating systems, etc. ARSENE  aims to accelerate the research and development of sovereign, industrializable security solutions. Outcomes will include ASIC and FPGA demonstrators.


  • Project name: CAOTIC (Collaborative Action on Timing Interference)
  • ANR project
  • October 2022 to October 2026
  • Project CAOTIC is an ambitious initiative aimed at pooling and coordinating the efforts of major French research teams working on the timing analysis of multicore real-time systems, with a focus on interference due to shared resources. The objective is to enable the efficient use of multicore in critical systems. Based on a better understanding of timing anomalies and interference, taking into account the specificities of applications (structural properties and execution model), and revisiting the links between timing analysis and synthesis processes (code generation, mapping, scheduling), significant progress is targeted in timing analysis models and techniques for critical systems, as well as in methodologies for their application in industry. In this context, the originality and strength of the CAOTIC project resides in the complementarity of the approaches proposed by the project members to address the same set of scientific challenges: (i) build a consistent and comprehensive set of methods to quantify and control the timing interferences and their impact on the execution time of programs; (ii) define interference-aware timing analysis and real-time scheduling techniques suitable for modern multi-core real-time systems; (iii) consolidate these methods and techniques in order to facilitate their transfer to industry.


  • EUR CyberSchool + Région Bretagne
  • September 2021 – December 2024
  • Security of computing systems is a critical and highly topical issue. Numerous types of attack exist, and this project focuses on fault-injection attacks on embedded systems. These attacks are becoming a threat to systems that were previously spared: certain injection methods are now accessible to anyone, and fault injection software is being developed.
    The literature mainly deals with a single fault, but more and more works refer to the possibility of injecting multiple faults.  We have recently shown that, when precise and numerous faults are possible, a program in binary format can be attacked in many ways. In this preliminary work, exploits were performed manually. This work and the literature show the importance of a vulnerability analysis or attack path search at the binary level in the context of fault-based attacks.
    The objectives of this project are :

    1. to propose an automatic approach, based on static analysis, to determine possible exploits for an attacker model and a target, then to carry them out (in simulation or experimentation) on binary code, in order to achieve a given objective (writing data to a memory location, calling a function with given parameters, extracting data from the memory, etc.);
    2. propose a method for quantifying the level of vulnerability of a binary code, for example on the basis of the minimum number of faults required to perform an exploit, the nature of the faults, etc. ;
    3. propose software or hardware countermeasures to these attacks, and automate their deployment.

    The experiments will be based on a fault simulator developed by the PACAP team on the basis of gem5, but real injections can be carried out on various fault injection benches available to us (clock glitch, laser, etc.)


  • Dynamic vectorization for heterogeneous multi-core processors with single instruction set
  • ANR JCJC project
  • April 2020 to October 2023
  • Most of today’s computer systems have CPU cores and GPU cores on the same chip. Though both are general-purpose, CPUs and GPUs still have fundamentally different software stacks and programming models, starting from the instruction set architecture. Indeed, GPUs rely on static vectorization of parallel applications, which demands vector instruction sets instead of CPU scalar instruction sets. We advocate a disruptive change in both CPU and GPU architecture by introducing Dynamic Vectorization at the hardware level.Dynamic Vectorization will combine the efficiency of GPUs with the programmability and compatibility of CPUs by bringing them together into heterogeneous general-purpose multi-cores. It will enable processor architectures of the next decades to provide (1) high performance on sequential program sections thanks to latency-optimized cores, (2) energy-efficiency on parallel sections thanks to throughput-optimized cores, (3) programmability, binary compatibility and portability.


We are proud participants of the HiPEAC network of excellence, the European Network of Excellence on High Performance and Embedded Architecture and Compilation.

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