Simultaneous multithreading (SMT) is an interesting way of maximizing performance by enhancing processor utilization. Between 1993 and 1997, with S. Hily, have investigated various issues involving the behavior of the memory hierarchy with SMT: branch prediction, memory hierarchy behavior, out-of-order and in-order executions,.. Later (2004) with R. Dolbeau ,we have been exploring an intermediate design point between SMT and CMP, the CASH architecture (for Cmp And Smt Hybrid) which principles
are very similar to what has appeared in some recent designs. More recently with H. Vandierendonk, we explored instruction fetch policies for SMT.
- S. Hily, A. Seznec “ Branch prediction and simultaneous multithreading ”, 25 pages, IRISA Report No 997, March 1996. appears as in proceedings of PACT’96, Boston, october 1996.
- S. Hily, A. Seznec “ Standard Memory Hierarchy Does Not Fit Simultaneous Multithreading, Proceedings of MTEAC’98 Workshop, Feb. 1998 , a longer version is available as Contention on 2nd Level Cache May Limit The Effectiveness of Simultaneous Multithreading , 22 pages, IRISA Report No 1086, Feb. 1997
- S. Hily, A. Seznec “ Out-Of-Order Execution May Not Be Cost-Effective on Processors Featuring Simultaneous Multithreading ”, IRISA Report No 1179, March 1998, short version appears in proceedings of HPCA-5, Orlando, Jan. 1999.
- K. Luo, M. Franklin, S. Mukherjee, A. Seznec, “Boosting SMT Performance by Speculation Control”, Proceedings of International Parallel and Distributed Processing Symposium, april 2001
- R. Dolbeau, A. Seznec, “ CASH: revisiting hardware sharing in single-chip parallel processor “, IRISA Report, November 2002
- Hans Vandierendonck, Andre Seznec, “Fairness Metrics for Multi-Threaded Processors,” IEEE Computer Architecture Letters, vol. 99, Feb. 2011
- H. Vandierendonck, A. Seznec, “Managing SMT Resource Usage through Speculative Instruction Window Weighting“, ACM Transactions on Computer Architecture, October 2011.