Ultra-low power architectures

This research work aims at developing ultra low-power System on Chip for Wireless Sensor Nodes. Our goal is to be able to improve the energy efficiency of WSN by at least an order of magnitude compared to existing state of the art low power micro-controllers such as the TI’s MSP430. Our approach reduces the power consumption by combining hardware specialization and power gating techniques. Typical WSN applications consist of small to medium grain tasks that are implemented on a microcontroller using a featherweight OS (Contiki, TinyOS). Rather than implementing these tasks in software, we propose to map each of these tasks to their own specialized hardware structures that we call a hardware task (HT). Such an hardware task consists of a minimalist (and customized) data-path controlled by a finite state machine (FSM). By customizing each of these hardware implementations to the task at hand, we obtain a significant reduction of the dynamic power dissipated by the whole system. To circumvent the increase in static power caused by the possibly numerous HTs implemented in the chip, we combine our approach with power gating, so as to supply power to a HT only when it needs to be executed [PDS10d]. To validate the relevance of the approach, we have developed a complete system-level design flow supporting our architectural model. This flow takes as input a description of the behaviors of each micro- task in ANSI-C along with a model of the target platform (expressed using a custom Domain Specific Language). The flow produces as a result a fully synthesizable description of the whole system. The tool is implemented as a set of extensions to the Gecos compiler infrastructure and extensively uses leading edge Model Driven Software design tools and techniques.

  • A. Pasha, S. Derrien, and O. Sentieys, “System Level Synthesis for Wireless Sensor Node Controllers: A Complete Design Flow,” ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. 17, iss. 1, pp. 2.1–2.24, 2011.
  • M. A. Pasha, S. Derrien, and O. Sentieys, “A Complete Design-Flow for the Generation of Ultra Low-Power WSN Node Architectures Based on Micro-Tasking,” in Proc. of the 47th IEEE/ACM Design Automation Conference (DAC), Anaheim, CA, USA, 2010, pp. 693-698.

Wakeup Time and Wakeup Energy Estimation in Power-Gated Logic Clusters

Run-time power gating for aggressive leakage reduction has brought into focus the cost of mode transition overheads due to frequent switching between sleep and active modes of circuit operation. In order to design circuits for effective power gating, logic circuits must be characterized for overheads they present during mode

transitions. We have proposed a method to determine steady-state virtual-supply voltage in active mode and hence present a model for virtual-supply voltage in terms of basic circuit parameters. Further, we derived expressions for estimation of two mode transition overheads: wakeup time and wakeup energy for a power-gated logic cluster using the proposed model. Experimental results of application of the model to ISCAS85 benchmark circuits show that wakeup time may be estimated within a low average error across large variation in sleep transistor sizes and variation in circuit sizes with significant speedup in computation time compared to transistor-level circuit simulations.

  • V. D. Tovinakere, O. Sentieys, and S. Derrien, “A Semiemperical Model for Wakeup Time Estimation in Power-Gated Logic Clusters,” in Proc. of the 49th IEEE/ACM Design Automation Conference (DAC), San Francisco, CA, USA, 2012, pp. 48-55.
  • V. D. Tovinakere, O. Sentieys, and S. Derrien, “A Polynomial Based Approach to Wakeup Time and Energy Estimation in Power-Gated Logic Clusters,” Journal of Low Power Electronics (JOLPE), vol. 7, iss. 4, pp. 482-489, 2011.