Reconfigurable architecture design

Reconfigurable Architecture Modeling

Architectures supporting Dynamic and Partial Reconfiguration (DPR) are becoming increasingly complex in terms of both reconfiguration mechanism and embedded computing and storage resources. One of the major issue when designing such architectures is to be able to obtain a quick feed-back over proposed architectural choices. To address this problem, we have proposed a platform model for the definition of dynamically reconfigurable architectures (DRA) and their associated design tools.

Fault-Tolerant Reconfigurable Systems

The use of reconfigurable hardware in critical applications like transportation and transaction systems is increasing rapidly. Undetected errors caused e.g. by radiation may result in fatal silent data corruption and unreproducible system crashes. Since it is virtually impossible to build devices which are free from faults, it is essential to embed some sort of fault-tolerance in such devices, which will enable them to work correctly even in the presence of faults. Since the past decade, a lot of research has been done to develop fault-tolerant reconfigurable systems on various granularity levels, although most of them have dealt with the lowest level such as offered by FPGAs.

We have considered the possibility of implementing low-cost hardware techniques which would allow to tolerate temporary faults in the data-paths of coarse-grained reconfigurable architectures. Our goal was to use less hardware overhead than commonly used duplication or triplication methods.
To cope with the high sensitivity of electronic devices to failures or soft errors, we also proposed a multiprocessor system on an dynamically reconfigurable architecture for the design of fault-tolerant systems. First we have proposed and designed a flexible communication model which ensures reliable communication. This work permits to switch from a communication protocol, by reconfiguring the reserved zone for the communication protocol, to a secondary one in order to mitigate communication errors. Some possibilities to integrate this dynamic platform into standardized automotive software infrastructure have also been introduced.
In order to exploit the computational power and the flexibility of reconfigurable architecture, and at the same time to guarantee the  correct functionality of the entire system, we proposed a fully dynamic MPSoC topology. In this system, all the processors can be dynamically reconfigured, moved or replaced in the system, hence providing fault-tolerant and self-repair capability. A deep exploration of a standard design flow has been done to facilitate the design of this architecture using commercially available FPGAs.

Management of Dynamically Reconfigurable Systems

To support the dynamic behavior of new embedded applications, heterogeneous execution resources are often included in modern MPSoC (Multi-Processor System-on-Chip) systems. The management of these resources is typically supported by an operating system (OS) that includes specific services for the scheduling and placement of tasks within the reconfigurable resources, along with inter-task communication management. The classical scheduling problem is then extended with a spatial dimension to manage the physical available area into the reconfigurable resource. We have therefore proposed a scheduling algorithm based on Artificial Neural Networks (ANN). The scheduling was moreover extended with task placement on heterogeneous reconfigurable execution resource by defining a spatio-temporal scheduling. Finally, we have proposed an area efficient hardware implementation of the neural network used in our scheduler. This implementation demonstrates the relevance of a hardware implementation of the service.

Flexible Communication Infrastructure

To support task communications within reconfigurable resources, we have proposed a specific inter- connection architecture, that is well-suited to dynamic and partial reconfiguration. We also defined specific communication services to support data exchanges between hardware and/or software tasks. This service can be seen as a middleware service managing data transfers (send, receive) without any information about the actual task placement on the platform. This drastically simplifies the application development and provides a unified communication interface for all tasks. A demonstrator platform has been prototyped to illustrate our concept of communication network re- configuration. To support the communication constraints required by dynamic reconfiguration, we have proposed the DRAFT Network-on-Chip (NoC), a NoC based on a fat-tree topology. Thanks to the ability to automatically generate DRAFT simulation and synthesis models, we were able to com- pare our model against other popular NoC topologies, such as mesh and regular fat-tree.