Software and Hardware


The Gecos (Generic Compiler Suite) project is an open source compiler infrastructure developed in the CAIRN group since 2004. Gecos was initially designed so as to address part of the shortcomings of existing C/C++ infrastructures such as SUIF. Its main characteristics are highlighted below:

  • GeCoS is a C compiler infrastructure entirely written in Java following Model Driven Engineering design principles. In particular Gecos leverage on the Eclipse Modeling Framework (EMF) and uses Eclipse as an underlying infrastructure and thus take benefits of its plugin mechanism to be easily extensible.
  • GeCoS is targeted to Application Specific Processors (ASIPs) design and Custom Hardware Accelerator Synthesis. It includes partial C++ support to accommodate with bit-accurate datatypes (our front-end support Mentor Graphic Algorithmic C Datatypes C++ templates).
  • GeCoS can be used as a Source to Source compiler (see the S2S4HLS project
    or as a standalone flow with a complete retargetable compiler back-end (customizable BURG based instruction selection, a flexible register allocator), and support for hardware synthesis (see the LOMITA framework).

Orcc is a development environment under BSD license dedicated to dataflow programming. Its primary purpose is to provide developers with a compiler infrastructure to allow several languages (software and hardware) to be generated from the same description composed of RVC-CAL actors and XDF networks. Orcc does not generate assembly or executable code directly, rather it generates source code that must be compiled by another tool.
Orcc is the result of a collaborative work between several academic institutions and innovating companies. IRISA-CAIRN contribution comes from Hervé Yviquel’s work.

ID.Fix is a source to source tool which convert a C source code specified with floating data type to a C/C++ source code specified with fixed-point data type based on a analytical approach. ID.Fix is developed by the INRIA/IRISA as part of a joint collaboration with STMicroelectronics. ID.Fix is developed in the GeCoS frameworkGeCoS (Generic Compiler Suite) is an open source compiler infrastructure.


Integrated Circuitsochre-v2-layout

  • OCHRE V1 : on-chip randomness extraction (1 mm2 130nm technology, fabricated in January 2009), successfully tested
  • OCHRE V2 : true random number generator with on-line randomness quality monitoring (4 mm2 130 nm technology, fabricated in May 2010), successfully tested
  • Express Chip : low-power circuit for digital radio (65 nm technology, fabricated in May 2011)
  • eFPGA : custom dynamically reconfigurable FPGA logic fabric (65 nm technology, under fabrication, expected for October 2013)


  • Zyggie: BAN Platform for Motion Capture  (developped in the BoWI project)
    Demo video
  • PowWow: Power Optimized Hardware and Software FrameWork for Wireless MotesPowWowRcup