HARDIESSE

Inria international program

Heterogeneous Accelerators for Reconfigurable DynamIc, Energy efficient, and Secure SystEms

Annual report (2014+2015)

 

Associate Team acronym: HARDIESSE

Period of activity: 2014 – 2016, 1st and 2nd year

Principal investigator (Inria): Olivier SENTIEYS, INRIA Rennes-Bretagne Atlantique, Cairn

Principal investigator (partner): Russel TESSIER, University of Massachusetts at Amherst

Other participants: Arnaud TISSERAND, CNRS, Cairn, Steven DERRIEN, UR1, Cairn, Maciej CIESIELSKI, University of Massachusetts at Amherst

1.    Abstract of the scientific program  

Rapid evolutions of applications and standards require frequent in-the-field system modifications and thus strengthen the need for adaptive devices. This need for a strong flexibility, combined with technology evolution (and the so-called power wall) has motivated the surge towards the use of multiple processor cores on a single chip (MPSoC). While it is now clear that we have entered the multi-core era, it is however indisputable that, especially for energy-efficient embedded systems, these architectures will have to be heterogeneous, by combining processor cores and specialized accelerators. We foresee a need for systems able to continuously adapt themselves to changing environments where software updates alone will not be enough for tackling energy management and error tolerance challenges. We believe that a dynamic and transparent adaptation of the hardware structure is the key to success. Security will also be an important challenge for embedded devices. Protections against physical attacks will have to be integrated in all secured components. In this Associated Team, we study new reconfigurable structures for such hardware accelerators with specific focus on energy efficiency, runtime dynamic reconfiguration, security, and verification.

Our research is organized into four main topics:

A. Dynamic reconfiguration support in FPGA

Almost since the creation of the first SRAM-based FPGAs there has been a desire to explore the benefits of partially reconfiguring a portion of an FPGA at run-time while the remainder of design functionality continues to operate uninterrupted. Currently, the use of partial re- configuration imposes significant limitations on the FPGA design: reconfiguration regions must be constrained to certain shapes and sizes and, in many cases, bitstreams must be precompiled before application execution depending on the precise region of the placement in the fabric. We plan to develop an FPGA architecture that allows for seamless translation of partially-reconfigurable regions, even if the relative placement of fixed-function blocks within the region is changed.

B. Power optimizations of reconfigurable architectures

Given the tight power and energy constraints that embedded systems have to satisfy nowadays, low power optimizations of reconfigurable architectures are a key concern. Recent works in Cairn led to early prototypes of wireless sensor nodes using either hardware specialized micro-tasks [PDS11, TSD12] and more recently reconfigurable hardware, both with a very-high energy efficiency but still limited to control intensive tasks. The objective of this work is therefore to extend these concepts to data-intensive tasks and to work on strong power optimization of reconfigurable data-paths and memory hierarchies.

C. Verification of large arithmetic circuits

With the ever-increasing size and complexity of integrated circuits (IC) and systems on chip (SoC), design verification has become a dominating factor of the overall design flow. Particularly important and challenging is verification of datapaths and their arithmetic components. Current formal verification techniques are largely ineffective when dealing with large arithmetic designs as they rely on established Boolean techniques that require flattening the entire design into bit-level netlists. This is a problem for IC and SoC verification with intensive arithmetic computations based on large and complex operators (not only adders and multipliers, but also dividers and function approximations).

D. Hardware support for security

Security is a critical issue not only for payment mechanisms and access control, but also for network communications. Transferring secure information at high speeds, under real-time constraints, is a great challenge. In every situation, there are compromises between speed, security, and cost; a risk assessment is necessary to determine the level of security required. Hardware cryptography provides a very fast way of encrypting and/or signing messages and network elements.

  • [PDS11] A. Pasha, S. Derrien, and O. Sentieys, “System Level Synthesis for Wireless Sensor Node Controllers: A Complete Design Flow,” ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. 17, iss. 1, pp. 2.1–2.24, 2011.
  • [PSD08] S. Pillement, O. Sentieys, and R. David, “DART: A Functional-Level Reconfigurable Architecture for High Energy Efficiency,” EURASIP Journal on Embedded Systems (JES), pp. 1-13, 2008.
  • [TSD12] V. D. Tovinakere, O. Sentieys, and S. Derrien, “A Semiemperical Model for Wakeup Time Estimation in Power-Gated Logic Clusters,” in Proc. of the 49th IEEE/ACM Design Automation Conference (DAC), San Francisco, CA, USA, 2012, pp. 48-55.
  • [PT12] D. Pamula and A. Tisserand. “GF(2^m) Finite-Field Multipliers with Reduced Activity Variations”. 4th International Workshop on Arithmetic of Finite Fields (WAIFI), July 2012. [HAL PDF]
  • [Tis07] A. Tisserand. “High-Performance Hardware Operators for Polynomial Evaluation”. Int. J. High Performance Systems Architecture, 1(1):14-23, March 2007. Note: Invited paper.
  • [BT13] K. Bigou and A. Tisserand. ” Improving Modular Inversion in RNS using the Plus-Minus Method”. 15th Workshop on Cryptographic Hardware and Embedded Systems (CHES), August 2013. [HAL PDF]
  • [CT13] T. Chabrier and A. Tisserand. “On-the-Fly Multi-Base Recoding for ECC Scalar Multiplication without Pre-Computations“. ARITH 21: IEEE Symposium on Computer Arithmetic, April 2013. [HAL PDF]
  • [CBR13] M. Ciesielski, W. Brown, A. Rossi, “Arithmetic Bit-level Verification using Network Flow Model”, Haifa Verification Conference, HVC-2013, Nov. 2013.
  • [BTRC11] M.A. Basith, T. Ahmad, A. Rossi, M. Ciesielski, “Algebraic Approach to Arithmetic Design Verification” Formal Methods in CAD, FMCAD-11, pp. 67-71, Oct/Nov 2011.
  • [UCTW13] K. Hu, H. Chandrikakutty, R. Tessier, and T. Wolf, Scalable Hardware Monitors to Protect Network Processors from Data Plane Attacks, in the Proceedings of the IEEE International Conference on Communications and Network Security, Washington, DC, October 2013.
  • [CUTW13] H. Chandrikakutty, D. Unnikrishnan, R. Tessier, and T. Wolf, High-Performance Hardware Monitors to Protect Network Processors from Data Plane Attacks, in the Proceedings of the IEEE/ACM Design Automation Conference, Austin, TX, June 2013.
  • [YULGT11] D. Yin, D. Unnikrishnan, Y. Liao, L. Gao, and R. Tessier, Customizing Virtual Networks with Partial FPGA Reconfiguration, in ACM Computer Communication Review, January 2011, vol. 41, no. 1., January 2011, pp. 125-132.

2.    Scientific progress

A. Dynamic reconfiguration support in FPGA

Virtual Bit-Stream: Compressed and Runtime Relocatable FPGA Configurations. The self-reconfiguration capabilities of modern FPGA architectures pave the way for dynamic applications able to adapt to transient events. The CAD flows of modern architectures are nowadays mature but limited by the constraints induced by the complexity of FPGA circuits. In Christophe Huriaux’s thesis [Hur15], multiple contributions are developed to propose an FPGA architecture supporting the dynamic placement of hardware tasks. First, an intermediate representation of these tasks configuration data, independent from their final position, is presented. This representation allows to compress the task data up to 11× with regard to its conventional raw counterpart [HCS15]. An accompanying CAD flow, based on state-of-the-art tools, is proposed to generate relocatable tasks from a high-level description. Then, the online behavior of this mechanism is studied. Two algorithms allowing decoding and creating in real-time the conventional bit-stream are described. In addition, an enhancement of the FPGA interconnection network is proposed to increase the placement flexibility of heterogeneous tasks, at the cost of a 10% increase in average of the critical path delay. Eventually, a configurable substitute to the configuration memory found in FPGAs is studied to ease their partial reconfiguration. Russell Tessier will participate in Christophe Huriaux’s Ph.D. defense jury as an examiner in December 2015 and discuss its latest work with the CAIRN team during his one-week visit.

FPGA Architecture Support for Heterogeneous, Relocatable Partial Bitstreams. The use of partial dynamic reconfiguration in FPGA-based systems has grown in recent years as the spectrum of applications which use this feature has increased. For these systems, it is desirable to create a series of partial bitstreams which represent tasks which can be located in multiple regions in the FPGA fabric. While the transferal of homogeneous collections of lookup-table based logic blocks from region to region has been shown to be relatively straightforward, it is more difficult to transfer partial bitstreams which contain fixed-function resources, such as block RAMs and DSP blocks. In this work we consider FPGA architecture enhancements which allow for the migration of partial bitstreams including fixed-function resources from region to region even if these resources are not located in the same position in each region. Our approach does not require significant, time-consuming place-and-route during the migration process. We quantify the cost of inserting additional routing resources into the FPGA architecture to allow for easy migration of heterogeneous, fixed-function resources. Our experiments show that this flexibility can be added for a relatively low overhead and performance penalty. This work was performed first during Russell Tessier’s visit in France during 2013 and continued during Christophe Huriaux’s visit at UMASS in summer 2014 and has been published as a poster at IEEE/ACM FCCM 2014 (Boston) [HST14p] and as a full paper at IEEE FPL 2014 (Munich) [HST14].

B. Power optimizations of reconfigurable architectures

Hybrid-JIT: Hardware/Software dynamic compilation for low-power adaptive computing. It is now acknowledged that the efficiency of Dynamic Voltage Frequency Scaling techniques is rapidly decreasing with new process nodes. Runtime management of energy vs. performance trade-offs will have to be handled at the micro-architectural level (e.g as in ARM Big.Little processors). This work proposes a new approach to the problem in the form of a run-time adaptive VLIW processor in which energy/performance trade-offs are managed through a combination of reconfigurable hardware and hardware-accelerated dynamic compilation. Our approach has been validated as an FPGA prototype, and demonstrates significant energy saving potential w.r.t existing approaches. This work was performed by Simon Rockiki and Steven Derrien and is currently under review [RDR15]. Steven Derrien visited UMASS in December 2014 and Simon Rockiki visited UMASS from January to July 2015.

Low Power Reconfigurable Controllers for Wireless Sensor Network Nodes. A key concern in the design of controllers in wireless sensor network (WSN) nodes is the flexibility to execute different control tasks involving sensing, communications and computational resources of the node. In this work, low power flexible controllers for WSN nodes based on reconfigurable microtasks composed of an FSM and datapath were studied. Coarse grain power gating opportunities are exploited in FSM and datapath for low power operation in reconfigurable microtasks. Power estimation results on typical benchmark microtasks show a 2x to 5x improvement in energy efficiency w.r.t a microcontroller at a cost of 5× relative to a microtask implemented as an ASIC with higher NRE costs [DSDH14].

C. Verification of large arithmetic circuits

There was no activity in this topic in 2015. Collaborations are expected to start in 2016 during next visits at UMASS.

D. Hardware support for security

CPU Diversification: Combined Hardware-Assisted and Software-Assisted Obfusca-tion for Low-Cost Devices. In embedded systems, the storage of binary code on untrusted memory (e.g. memory that can be read or modified by external attacker) is a major concern. Indeed, by reverse-engineering this code, one can clone the (proprietary) code, insert malware or provoke a denial of service. Existing techniques are based on software transformations (of the control-flow graph structure), which makes the reverse-engineering more challenging. The main idea of our work is to modify the CPU used in such a system in order to remove information to the attacker. Indeed, if the attacker does not know anything about the processor used, reverse-engineering the binary code will be much more challenging. One particular point we worked on was the modification of the CPU instruction set. Indeed, by changing the way different instructions are encoded, we have a deep impact on binaries. We performed the following modifications:

  • modification of the value of different opCodes;
  • placement of different bits inside the 32-bit instruction;
  • suppression of several instructions (as long as we keep a sufficient subset of the original instructions set);
  • addition of redundancy inside opCode utilization in order to prevent the identification of some instructions using their frequency inside the code.

All of these transformations will affect the CPU decoding stage and lead to a negligible loss of performance/area on the chip.

The idea was implemented on a MIPS processor in order to measure exactly the impact of different transformations. We use a modified compilation tool-chain to generate our binaries using both existing software techniques and our developed transformation. We are currently performing a statistical analysis of the generated binaries trying to measure how stronger the generated code is. This work was performed during the visit of Simon Rokicki at UMASS in 2015, in collaboration with Russell Tessier, and with Marc Fyrbiak and Christof Paarfrom from Ruhr-Universität Bochum, Germany [FPTR16].

Securing FPGA-based Cryptographic Primitives. Over the past five years, the security of SRAM-based FPGA bitstreams has primarily been provided by bitstream encryption. Recently, however, the effectiveness of this security approach has been brought into question, raising the possibility of logic-level design exposure. Although contemporary FPGAs can contain millions of lookup tables providing some ambiguity, the identification and modification of specific structural components, such as encryption cores, is a concern. In this work, we demonstrate that AES can be easily identified in a LUT-level design for a variety of implementation styles which are independent of FPGA cluster architecture. Our graph-based approach considers AES implementations created using a variety of synthesis and technology mapping options. To address this issue we present countermeasures which allow for the configuration of security primitives after the security primitive is loaded into the FPGA device. As a result, it is not possible to identify and modify security primitives by searching for them in the reverse engineered bitstream. These countermeasures are well-hidden in the LUT-level design and add a limited amount of logic and energy consumption to the underlying design. We quantify this overhead and demonstrate the effectiveness of the countermeasures on a Virtex 5 FPGA. This work was performed during Christophe Huriaux’s visit at UMASS in summer 2014 and has been published in the IEEE/ACM FCCM conference in May 2015 [SFPH+15].

Asymmetric cryptographic resources for high-security network routers. During the second year of the project, we worked on the design and implementation of a complete ECC (elliptic curve cryptography) and HECC (hyper-elliptic curve cryptography) crypto-processor with very limited resources. This crypto-processor includes finite-field arithmetic units over GF(p), a register file for point coordinates, a key recoding unit, a controller (based on a microcode instruction set) and an external interface (based on an ARM dual-core processor interfaceD on a Zynq FPGA). The obtained crypto-processor is very small and efficient. To the best of our knowledge, this is the first programmable processor for HECC (A. Tisserand has been invited speaker at ECC 2015 [Tis15], the major event on elliptic and hyper-elliptic curve cryptography). Our crypto-processor has been presented at Compas 2015 [GTV15].

Our crypto-processor and its programming tool/library will be released under hardware/software open-source and used for the collaboration in the project (up to now there is no equivalent open-source solution).

We added several protections against side channel attacks to our crypto-processor. First, we have the first published on-the-fly hardware recoding for ECC and HECC using Euclidean addition chains (published at Compas 2015 [PTVM15]. This specific type of recoding only requires point additions (and no more point doublings). Then it is naturally protected against Simple Power Attacks (SPA). Up to now, recoding EACs from binary scalars on-the-fly was not considered possible and efficient. Our proposition leads to up to 18% speedup compared to state-of-the-art SPA protected solutions for ECC.

We also worked on a new RNS (residue number system) algorithm for fast modular multiplication in ECC. Our new algorithm has been implemented on FPGA and it reduces the area of the crypto-processor by a factor of 2 for a small timing overhead (at most 4%). This new result has been accepted and presented at CHES 2015 [BT15].

3.    Next year’s work program

A. Dynamic reconfiguration support in FPGA

We plan to continue our research on an FPGA architecture which allows for easy translation of partially-reconfigurable regions even if the relative placement of fixed-function blocks within the region is changed. This topic was mainly covered by the PhD thesis of C. Huriaux who will visit again UMASS in 2016.

  • Common work on the bitstream architecture to support dynamic reconfiguration.
  • Extension of the paper at FPL 2014 for a journal paper (IEEE Trans. VLSI Syst.).
  • Visit of 2 CAIRN members (O. Sentieys, 2 weeks, C. Huriaux, 2 weeks) for a period of one month.
  • Visit of 1 UMASS Professor (R. Tessier, 1 month, shared with Topic D) to work with Olivier Sentieys and Christophe Huriaux on enhancing dynamic reconfiguration efficiency in FPGA and to write the final version of the paper before submission. Russel Tessier will be an invited Professor (UR1-ENSSAT) for 1 month in June/July.
  • Visit of 1 PhD student from UMASS (1 month) to learn about the embedded FPGA developed by CAIRN and to work on a common topic.

B. Power optimizations of reconfigurable architectures

Two main techniques can be used for a significant reduction of energy in CMOS chips: firstly, when considering static power due to current leakage in transistors, power gating – i.e. cutting-off the power supply of a logic cluster – can be used when the gates are not active; and secondly voltage scaling of the power supply (Vdd), together with a chip frequency scaling, gives quadratic (or even more) gains in the dynamic and static power consumption and can still be used while the chip is running. Moreover, Using Fully Depleted Silicon-On-Insulator (FDSOI) devices in cutting-edge technologies such as 28nm significantly improves the trade-off between leakage, variability and speed even at very low-voltage. FDSOI enables to reduce leakage power up to 10X using Reverse Body Biasing. We will study a heterogeneous SoC with coarse-grain reconfigurable hardware accelerators taking advantage of power gating, dynamic power management (voltage, frequency), and asynchronous communications for decreasing both dynamic and static power consumption. After defining the micro-architecture and the memory hierarchy, some transistor-level and layout-level design and simulation with CAD tools will be performed to characterize precisely both performance and energy. In case of encouraging results, some prototype chips can moreover be designed and fabricated using an advanced 28nm FDSOI technology. This topic is covered by the PhD thesis of R. Ragavan who will visit UMASS in 2016.

  • Common work on power models of reconfigurable architecture including dynamic reconfiguration.
  • Common work on power optimizations of the embedded FPGA developed by CAIRN and on power optimization of coarse-grain reconfigurable architectures.
  • Visit of 1 PhD student (R. Ragavan) for a period of 1 month on power optimizations of the embedded FPGA developed by CAIRN.
  • Visit of 1 PhD student from UMASS (1 month) to work on integrating power models suitable for the embedded FPGA in the VPR toolflow.

C. Verification of large arithmetic circuits

The goal of this collaborative research is to overcome the limitations of current verification methods and to develop techniques that will be efficient and scalable to large arithmetic designs. It will use a new approach, from UMASS, to functional verification of arithmetic bit-level circuits [CBR13, BTRC11] by modeling it as a network flow problem. In the proposed approach, the computation performed by the arithmetic circuit is viewed as a flow of binary data in the network. The verification problem is cast as a suitably modified network flow problem in such a network and solved using symbolic term rewriting and linear algebraic techniques. The proposed technique will be applicable to complex arithmetic circuits, such as newly developed and bit-optimized adders, large multipliers, dividers, ALUs and MAC unit, and other components of combinational and sequential data paths implementing complex instructions. We will also work on the verification of arithmetic operators for function evaluation (sine, cosine, exponential, logarithm, etc.) based on polynomial approximations dedicated to hardware implementations.

  • CAIRN members have to learn the verification method and tools developed at UMASS. Bibliography study and training during a visit of 1 CAIRN member at UMASS (A. Tisserand, 1 week).
  • UMASS researchers have to learn algorithms and representations of numbers used in large advanced arithmetic operators (large multipliers, dividers, square-rooters, polynomial function approximations, etc.). Bibliography study and training during a visit of 1 UMASS Professor (M. Ciesielski, 1 week) and of 1 PhD student (1 month) at CAIRN.
  • Common work on verification methods for large arithmetic operators. Preparation of a common article for submission to a conference at the end of the year.
  • Common selection of target application examples to be used as benchmarks and development test cases.

D. Hardware support for high security network routers

We will work on the use of hardware accelerators for cryptographic primitives (designed at CAIRN) in hardware security layer of network routers (designed at UMASS). We plan to work on two complementary sub-topics: (1) Increased security of network routers, including multicore network processors. We will develop a way of sharing encryption/signature cores across several network processor cores in a network router. The small size and flexibility of the encryption core would be a key. (2) Increased FPGA security. FPGA circuits are used in many network elements due to their flexibility and small cost design cost (compared to ASICs). Making circuits synthesized for FPGA implementation difficult to identify. The idea would involve masking the functionality of a specific FPGA circuit (e.g. a processor core) to make it more difficult for an attacker. It is becoming easier to reverse engineer an FPGA bitstream so this approach would provide another line of defense.

  • CAIRN members will adapt the hardware accelerator for elliptic curve cryptography (ECC) designed at CAIRN in the ANR PAVOIS project (http://pavois.irisa.fr/) in order to provide the symmetric cryptography support for the collaboration. 1 CAIRN member (A. Tisserand) will visit UMASS.
  • Visit of 1 UMASS Professor (R. Tessier, 1 week, shared with Topic A) to work on the use of hardware security/cryptographic blocks in network routers.
  • Common work on the use of hardware security/cryptographic blocks in network routers and FPGA bitstream protection. Preparation of a common article for submission to a conference at the end of the year.
  • Common work on the use of cryptographic blocks to protect the routers against side channel attacks. Thanks to our new attack system (with electromagnetic radiation analysis), we will be able to evaluate different algorithms and architecture for router firmware in the case of side channel attacks.

4.    Record of activities

  • Christophe Huriaux visited UMASS for 3 months from May to August 2014. The grant for the visit was supported by UMASS while Inria supported the travel expenses.
  • Christophe Huriaux attended IEEE FCCM 2015 in Boston.
  • Olivier Sentieys attended IEEE/ACM ICCAD 2014 in San José where he met some of the colleagues from UMASS and discussed on common research work.
  • Steven Derrien visited UMASS for 1 week in December 2014.
  • Simon Rokicki visited UMASS for 6 months from January 2015 to July 2015.
  • Russell Tessier will visit INRIA for 1 week in December 2015.
  • Guy Lemieux, a Professor from University of British Columbia, Vancouver, Canada, will visit INRIA for 10 days. Guy Lemieux, a well-known specialist in FPGA, was introduced to us by Russell Tessier. This is a good opportunity for new collaborations. He will be a reviewer and a committee member of Christophe Huriaux’s PhD thesis.

5.    Production

[DSDH14] Vivek Tovinakere Dwarakanath, Olivier Sentieys, Steven Derrien, Christophe Huriaux “Low Power Reconfigurable Controllers for Wireless Sensor Network Nodes,” IEEE 22nd Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), pp.230-233, 11-13 May 2014.

[HST14p] Christophe Huriaux, Olivier Sentieys, Russell Tessier, “FPGA Architecture Enhancements to Support Heterogeneous Partially Reconfigurable Regions,” IEEE 22nd Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), Poster, pp. 30, 11-13 May 2014.

[HST14] Christophe Huriaux, Olivier Sentieys, Russell Tessier, “FPGA architecture support for heterogeneous, relocatable partial bitstreams,” 24th International Conference on Field Programmable Logic and Applications (FPL), pp.1-6, 2-4 Sept. 2014.

[HCS15] Christophe Huriaux, Antoine Courtay and Olivier Sentieys, “Virtual Bit-Stream: A Design Flow for Compressed and Runtime Relocatable FPGA Configurations,” IEEE/ACM Design Automation and Test in Europe, 2015.

[Hur15] Christophe Huriaux, “Enhanced FPGA Architecture and CAD Flow for Efficient Runtime Hardware Reconfiguration”, Ph.D. thesis, University of Rennes I, 2015.

[SFPH+15] Pawel Swierczynski, Marc Fybriak, Christof Paar, Christophe Huriaux, Meha Kainth, Abhishek Kumar, Russell Tessier, “Protecting against Cryptographic Trojans in FPGA”, IEEE 23rd Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), pp. 151-154, 2-6 May 2015.

[RDR15] Simon Rokicki, Steven Derrien, Erven Rohou, “Hybrid-JIT: Hardware/Software Dynamic Compilation for Low Power Adaptive Computing,” submitted to ACM TACO.

[BTR14] F. Bucheron, A. Tisserand and L. Rilling.  “Hardware/Software Support for Securing Virtualization in Embedded Systems”. 1st Symposium on Digital Trust in Auvergne (SDTA), December 2014.

[CTPC14] J. Chen, A. Tisserand, E. Popovici and S. Cotofana. “Robust Sub-Powered Asynchronous Logic”. 24th International Workshop on Power And Timing Modeling, Optimization and Simulation (PATMOS), September 2014.

[BT14] K. Bigou and A. Tisserand. “RNS Modular Multiplication through Reduced Base Extensions”. 25th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), June 2014.

[PVTM15] J. Proy, N. Veyrat-Charvillon, A. Tisserand and N. Meloni. “Full Hardware Implementation of Short Addition Chains Recoding for ECC Scalar Multiplication”. Actes Conférence d’informatique en Parallélisme, Architecture et Système (ComPAS), 2015.

[GTV15] G. Gallin, A. Tisserand and N. Veyrat-Charvillon. “Comparaison expérimentale d’architectures de crypto-processeurs pour courbes elliptiques et hyper-elliptiques”. Actes Conférence d’informatique en Parallélisme, Architecture et Système (ComPAS), 2015.

[Tis15] A. Tisserand. “Hardware Accelerators for ECC and HECC”. 1th Workshop on Elliptic Curve Cryptography (ECC), Invited talk, 2015.

[BT15] K. Bigou and A. Tisserand. “Single Base Modular Multiplication for Efficient                   Hardware RNS Implementations of ECC”. Proc. 17th International Workshop on Cryptographic Hardware and Embedded Systems (CHES), 2015.

[FPTR16] Marc Fyrbiak, Christof Paar, Russel Tessier, and Simon Rokicki, CPU Diversification: Combined Hardware-Assisted And Software-Assisted Obfuscation for Low-Cost Devices, to be submitted.