eFPGA has been fabricated and delivered on the 3rd of April 2014
A newly developed circuit, an embedded FPGA, has been sent to fab in June 2013 (effective fabrication in October). This chip is closely related to the FlexTiles project, as it features a custom dynamically reconfigurable FPGA logic fabric laying down University of Rennes 1’s contribution to this FP7 project.
For this design, ST Microelectronics bulked CMOS 65nm technology has been chosen for the manufacturing process in their facility in Grenoble. We used CMP prototyping services for integration of eFPGA in a multiproject wafer.
The development of this chip is the result of months of development by the CAIRN team: Olivier Sentieys, Christophe Huriaux, Philippe Quémerais, Raphaël Bardoux, Rengarajan Ragavan and Amith Pai put their efforts in common to drive this project till the end.
The final integrated circuits will be used by the CAIRN team as a test platform to implement dynamic reconfiguration manager algorithm in the FlexTiles project, as well as to demonstrate our knowledge in FPGA design.
Chip Pictures
Layout
Legend : eFPGA, a die of 2.20X1.97mm in cmos 65nm
