On April 16th,, PhD student from our team and the CEA, will present us his thesis topic.
Title: Circuit partitioning for multi-FPGA platforms
An FPGA (‘Field Programmable Gate Array’) is an integrated circuit comprising a large number of programmable and interconnectable logic resources, which allow one to implement, by programming, a digital electronic circuit such as a microprocessor, a compute accelerator or a complex hybrid system-on-chip. FPGAs are widely used in the field of integrated circuits design, because they allow one to obtain prototype circuits very quickly, without having to manufacture the chip on silicon. However, some circuits are too big to be implemented on a single FPGA. To address this issue, it is possible to use a platform consisting of several highly interconnected FPGAs, which can be seen as a single virtual FPGA giving access to all the resources of the platform. This solution, although elegant, poses several problems. In particular, the existing tools do not account for all the constraints of the placement problem to be solved in order to efficiently map a circuit onto a multi-FPGA platform. For example, current cost functions are not designed to minimize signal propagation times between FPGA registers, nor do they take into account the capacity constraints induced by the routing of connections.