The objective of this tutorial is to put into perspective the role of deadlines in the design and analysis of critical embedded systems as well as to propose and discuss alternatives.

In current industrial practice, deadlines are used to isolate the control design process from the timing verification process. The control engineer can then work with idealized timing assumptions while the timing architect focuses on establishing that the specified deadline (derived from the sampling period) is always met. This use of deadlines as the interface between control and timing presents several limitations. First, the functional behavior of a system is influenced by timing effects such as sampling jitter even if deadlines are met. Second, and more importantly, requiring all deadlines to be met is an unnecessarily strong requirement.

There is a need for a more efficient approach to the co-design of industrial control applications between control engineering and real-time systems engineering. The purpose of this tutorial is to motivate and present state of the art and recent results in this direction. The invited speakers are academics and practitioners who are recognized experts in control and/or real-time systems design and verification working with new interfaces between these two worlds.