Contact information
INRIA Campus de Beaulieu 35042 RENNES Cedex FRANCE e-mail: pierre.michaud@inria.fr
About me
I am Chargé de Recherche at Inria in Rennes in the PACAP team. My research area is microarchitecture and microarchitecture modeling.
Papers
- P. Michaud, A. Peysieux, “HAIR: halving the area of the integer register file with odd/even banking“, ACM Transactions on Architecture and Code Optimization, vol. 19, no. 4, december 2022.
- P. Michaud, “PIPS: prefetching instructions with probabilistic scouts“, First Instruction Prefetching Championship, 31 may 2020. Slides.
- P. Michaud, “Exploiting thermal transients with deterministic turbo clock frequency“, IEEE Computer Architecture Letters, vol. 19, no. 1, march 2020.
- P. Michaud, “A simple model of processor temperature for deterministic turbo clock frequency“, Inria research report RR-9308, december 2019.
- P. Michaud, “An alternative TAGE-like conditional branch predictor“, ACM Transactions on Architecture and Code Optimization, vol. 15, no. 3, october 2018. BATAGE simulator.
- P. Michaud, “Some mathematical facts about optimal cache replacement“, ACM Transactions on Architecture and Code Optimization, vol. 13, no. 4, december 2016. HiPEAC 2017 slides.
- P. Michaud, “Best-offset hardware prefetching“, International Symposium on High-Performance Computer Architecture, march 2016. Slides. Download the paper from HAL, not from the IEEE site; IEEE messed up the PDF I sent them in 2016; for some reason unknown to me, they seem to have applied a script on the PDF that changed some numbers in the graphs.
- Mun-Kyu Lee, Pierre Michaud, Jeong Seop Sim, DaeHun Nyang, “A simple proof of optimality for the MIN cache replacement policy“, Information Processing Letters, Volume 116, Issue 2, february 2016.
- A. Sembrant, T. Carlson, E. Hagersten, D. Black-Schaffer, A. Perais, A. Seznec, P. Michaud, “Long term parking (LTP): criticality-aware resource allocation in OOO processors“, International Symposium on Microarchitecture, december 2015.
- P. Michaud, A. Mondelli, A. Seznec, “Revisiting clustered microarchitecture for future superscalar cores: a case for wide-issue clusters“, ACM Transactions on Architecture and Code Optimization, Volume 12, Issue 3, August 2015.
- P. Michaud, “A best-offset prefetcher“, 2nd Data Prefetching Championship, june 2015. Slides. First place.
- A. Perais, A. Seznec, P. Michaud, A. Sembrant, E. Hagersten, “Cost-Effective Speculative Scheduling in High Performance Processors“, International Symposium on Computer Architecture, june 2015.
- S. Eyerman, P. Michaud, W. Rogiest, “Revisiting symbiotic job scheduling“, International Symposium on Performance Analysis of Systems and Software, march 2015.
- S. Eyerman, P. Michaud, W. Rogiest, “Multi-program throughput metrics: a systematic approach“, ACM Transactions on Architecture and Code Optimization, Volume 11, Issue 3, October 2014. TPCalc software.
- P. Michaud, A. Seznec, “Pushing the branch predictability limits with the multi-poTAGE+SC predictor“, 4th JILP Workshop on Computer Architecture Competitions, Championship Branch Prediction (CBP-4), June 2014. Slides. Code. First place in unlimited size category.
- P. Michaud, “Five poTAGEs and a COLT for an unrealistic predictor“, 4th JILP Workshop on Computer Architecture Competitions, Championship Branch Prediction (CBP-4), June 2014. Slides. Code. Third place in unlimited size category.
- R. A. Velásquez, P. Michaud, A. Seznec, “BADCO: behavioral application-dependent superscalar core models”, International Journal of Parallel Programming, October 2013.
- R. A. Velásquez, P. Michaud, A. Seznec,”Selecting benchmark combinations for the evaluation of multicore throughput“, International Symposium on Performance Analysis of Systems and Software, April 2013.
- P. Michaud, “Constant-work multiprogram throughput metrics for microarchitecture studies“, INRIA report RR-8150, November 2012.
- P. Michaud, “Demystifying multicore throughput metrics“, IEEE Computer Architecture Letters, 2012.
- R. A. Velásquez, P. Michaud, A. Seznec, “BADCO: behavioral application-dependent superscalar core model”, 12th International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), 2012.
- P. Michaud, “Hardware acceleration of sequential loops“, INRIA report RR-7802, November 2011. Slides.
- P. Michaud, “Replacement policies for shared caches on symmetric multicores : a programmer-centric point of view“, 6th International Conference on High-Performance and Embedded Architectures and Compilers, January 2011. Technical report. Slides.
- P. Michaud, “The 3P and 4P cache replacement policies“, 1st JILP Workshop on Computer Architecture Competitions (JWAC-1), Cache Replacement Championship, June 2010. Slides. Code. Second place in single-core category, third place in multicore category.
- P. Michaud, Y. Sazeides, A. Seznec, “Proposition for a sequential accelerator in future general-purpose manycore processors and the problem of migration-induced cache misses“, ACM International Conference on Computing Frontiers, May 2010.
- P. Michaud, “Online compression of cache-filtered address traces“, IEEE International Symposium on Performance Analysis of Systems and Software, April 2009. slides. (ATC software).
- P. Michaud, “Periodic activity migration for fast sequential execution in future heterogeneous multicore processors“, November 2008, INRIA report RR-6735.
- S. Guntur, P. Michaud, “Decoupled thermal simulation“, IRISA report PI-1871, November 2007.
- P. Michaud, Y. Sazeides, A. Seznec, T. Constantinou, D. Fetis, “A study of thread migration in temperature-constrained multicores“, ACM Transactions on Architecture and Code Optimization, Volume 4, Issue 2, June 2007.
- P. Michaud, Y. Sazeides, “ATMI: Analytical Model of Temperature in Microprocessors“, Third Annual Workshop on Modeling, Benchmarking and Simulation (MoBS), June 2007. slides.
- P. Michaud, Y. Sazeides, “Scheduling issues on thermally constrained processors“, October 2006, INRIA report RR-6006.
- D. Fetis, P. Michaud, “An evaluation of HotSpot-3.0 block-based temperature model“, 5th Annual Workshop on Duplicating, Deconstructing, and Debunking (WDDD), June 18, 2006. slides.
- A. Seznec, P. Michaud, “A case for (partially) tagged geometric history length branch prediction“, The Journal of Instruction-Level Parallelism, Vol. 8, February 2006.
- P. Michaud, Y. Sazeides, A. Seznec, T. Constantinou, D. Fetis, “An analytical model of temperature in microprocessors“, INRIA report RR-5744, November 2005.
- T. Constantinou, Y. Sazeides, P. Michaud, D. Fetis, A. Seznec, “Performance Implications of Single Thread Migration on a Chip Multi-Core“, ACM SIGARCH Computer Architecture News, volume 33, issue 4, November 2005.
- P. Michaud. “A PPM-like , Tag-Based Branch Predictor“, The Journal of Instruction-Level Parallelism, Vol. 7, April 2005. First JILP Championship Branch Prediction Competition (CBP-1), 2004.
- P. Michaud, “Analysis of a tag-based branch predictor“, INRIA report RR-5366, November 2004.
- P. Michaud, “Exploiting the Cache Capacity of a Single-Chip Multi-Core Processor with Execution Migration”, 10th International Symposium on High Performance Computer Architecture, February 2004. slides
- P. Michaud, “A Statistical Model of Skewed Associativity”, International Symposium on Performance Analysis of Systems and Software, March 2003. slides
- P. Michaud, A. Seznec, “ A Comprehensive Study of Dynamic Global History Branch Prediction”, INRIA report RR-4219, June 2001.
- P. Michaud, A. Seznec, S. Jourdan, “An exploration of instruction fetch requirement in out-of-order superscalar processors”, International Journal of Parallel Programming, Vol.29 No.1, February 2001.
- P. Michaud, A. Seznec, “Data-Flow Prescheduling for Large Instructions Windows in Out-of-Order Processors”, 7th International Symposium on High Performance Computer Architecture, January 2001. slides
- P. Michaud, A. Seznec, S. Jourdan, “Exploring Instruction-Fetch Bandwidth Requirement in Wide-Issue Superscalar Processors”, International Conference on Parallel Architectures and Compilation Techniques, October 1999.
- P. Michaud, “Chargement des instructions sur les processeurs superscalaires“, PhD thesis (in french), November 1998.
- P. Michaud, A. Seznec, S. Jourdan, P. Sainrat, “Alternative Schemes for High-Bandwidth Instruction Fetching”, INRIA Report RR-3392, March 1998.
- P. Michaud, A. Seznec, R. Uhlig, “Trading Conflict and Capacity Aliasing in Conditional Branch Predictors”, Proceedings of the 24th International Symposium on Computer Architecture, June 1997. slides
- A. Seznec, S. Jourdan, P. Sainrat, P. Michaud, “Multiple-Block Ahead Branch Predictors”, Proceedings of the 7th Conference on Architectural Support for Programming Languages and Operating Systems, October 1996.
Software
- TPCalc – throughput calculator
- ATMI – microprocessor temperature model
- STiMuL – steady temperature in multi-layers
- ATC – address trace compressor
Course (in French)
Miscellaneous
- Effect of wire resistance on the bitline read delay in SRAMs
- Understanding the numbers that you get from your temperature model
- (Yet another) proof of optimality for MIN replacement
- The square-root law of instruction-level parallelism
