ADA 2024

Some information about the ADA master course

Contacts

    • André Seznec
      andre.seznec at inria.fr
      Microarchitecture, first 5 sessions
    • Caroline Collange
      caroline.collange at inria.fr
      GPU/accelerator architecture, 3 sessions
    • Simon Rokicki
      Simon.Rokicki at irisa.fr
      System-On-Chip, High-level synthesis, 5 sessions

Evaluation

      • 1h30 table exam : 13/11/2024
      • Written synthesis of a research paper + oral presentation: 2 sessions (04/11/ 2024 and 06/11/2024)

Slides

Schedule

  • 9/09, 11/09, 16/09,18/09, 23/09: A. Seznec
  • 25/09, 30/09, 2/10: C. Collange
  • 7/10, 9/10, 14/10, 16/10, 21/10: S. Rokicki

Articles to study (1 paper per student):

      • Write a critical synthesis of the paper (6 to 8 pages), to be sent to Andre.Seznec@inria.fr by 01/11/2024, 23:59:59
      • Prepare an oral presentation of the paper (presentation on 01/11/2024,  12 minutes + 3 minutes question)

Paper list (2024 list)

  1. Aniket Anand Deshmukh, Lingzhe Chester Cai, Yale N. Patt: Alternate Path Fetch. ISCA 2024: 1217-1229 Rami Sheikh, James Tuck, Eric Rotenberg: Control-Flow Decoupling. MICRO 2012: 329-340
  2. Glenn Reinman, Todd M. Austin, Brad Calder: A Scalable Front-End Architecture for Fast Instruction Delivery. ISCA 1999: 234-245
  3. Dean M. Tullsen, Susan J. Eggers, Joel S. Emer, Henry M. Levy, Jack L. Lo, Rebecca L. Stamm:Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor. ISCA 1996: 191-202
  4. Trevor E. Carlson (Uppsala University), Wim Heirman (Intel), Osman Allam (Ghent University), Stefanos Kaxiras (Uppsala University), and Lieven Eeckhout (Ghent University), The Load Slice Core Microarchitecture, ISCA 2015
  5. Whisper: Profile-Guided Branch Misprediction Elimination for Data Center Applications, Tanvir Ahmed Khan, Muhammed Ugur, Krishnendra Nathella, Dam Sunwoo, Heiner Litz, Daniel A Jiménez, and Baris Kasikci In Proceedings of the 55th International Symposium on Microarchitecture (MICRO), October, 2022.  https://web.eecs.umich.edu/~takh/papers/khan-whisper-micro-2022.pdf
  6. Morrigan: A Composite Instruction TLB Prefetcher,Georgios Vavouliotis, Lluc Alvarez, Boris Grot, Daniel A. Jimenez, Marc Casas. Proceedings of the 54th edition of the IEEE/ACM International Symposium on Microarchitecture (MICRO ’21). [pdf]
  7. Josipović, L., Ghosal, R., & Ienne, P. (2018, February). Dynamically scheduled high-level synthesis. In Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (pp. 127-136). http://dynamo.ethz.ch/wp-content/uploads/sites/22/2022/06/Josipovic_FPGA18_DynamicallyScheduledHighLevelSynthesis.pdf
  8. Derrien, S., Marty, T., Rokicki, S., & Yuki, T. (2020). Toward speculative loop pipelining for high-level synthesis. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 39(11), 4229-4239. https://univ-rennes.hal.science/hal-02949516/
  9. McFarlin, D. S., Tucker, C., & Zilles, C. (2013). Discerning the dominant out-of-order performance advantage: Is it speculation or dynamism?. ACM SIGARCH Computer Architecture News, 41(1), 241-252. http://zilles.cs.illinois.edu/papers/mcfarlin_asplos_2013.pdf
  10. Song Han, Xingyu Liu, Huizi Mao, Jing Pu, Ardavan Pedram, Mark A. Horowitz, William J. Dally. EIE: Efficient Inference Engine on Compressed Deep Neural Network
  11. Cheng, Jianyi, John Wickerson, and George A. Constantinides. “Probabilistic Scheduling in High-Level Synthesis.” 2021 IEEE 29th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM). IEEE, 2021. https://johnwickerson.github.io/papers/petrinets_fccm21.pdf
  12. Asiatici, M., & Ienne, P. (2019, February). Stop crying over your cache miss rate: Handling efficiently thousands of outstanding misses in fpgas. In Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (pp. 310-319). https://www.epfl.ch/labs/lap/wp-content/uploads/2019/06/AsiaticiFeb19_StopCryingOverYourCacheMissRateHandlingEfficientlyThousandsOfOutstandingMissesInFpgas_FPGA19.pdf
  13. Wang, Erwei, et al. “LUTNet: Rethinking inference in FPGA soft logic.” 2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM). IEEE, 2019. https://arxiv.org/pdf/1904.00938
  14. Dongho Ha, Yunho Oh, and Won Woo Ro. 2023. R2D2: Removing ReDunDancy Utilizing Linearity of Address Generation in GPUs. In Proceedings of the 50th Annual International Symposium on Computer Architecture (ISCA ’23). Association for Computing Machinery, New York, NY, USA, Article 4, 1–14. https://doi.org/10.1145/3579371.3589039 https://files.inria.fr/pacap/ada2020/Ha_R2D2_ISCA23.pdf
  15. Alexandru Duțu, Matthew D. Sinclair, Bradford M. Beckmann, David A. Wood, Marcus Chow. Independent Forward Progress of Work-groups. ISCA 2020 https://pages.cs.wisc.edu/~sinclair/papers/AWG_ISCA2020.pdf
  16. Vijay Kandiah, Daniel Lustig, Oreste Villa, David Nellans, and Nikos Hardavellas. 2023. Parsimony: Enabling SIMD/Vector Programming in Standard Compiler Flows. In Proceedings of the 21st ACM/IEEE International Symposium on Code Generation and Optimization (CGO 2023). Association for Computing Machinery, New York, NY, USA, 186–198. https://doi.org/10.1145/3579990.3580019
  17. Mhd Ghaith Olabi, Juan Gómez Luna, Onur Mutlu, Wen-mei Hwu, and Izzat El Hajj. 2022. A compiler framework for optimizing dynamic parallelism on GPUs. In Proceedings of the 20th IEEE/ACM International Symposium on Code Generation and Optimization (CGO ’22). IEEE Press, 1–13. https://doi.org/10.1109/CGO53902.2022.9741284 https://files.inria.fr/pacap/ada2020/Olabi_DynamicParallelism_CGO22.pdf
  18. ImPress: Securing DRAM Against Data-Disturbance Errors via Implicit Row-Press Mitigation
    Anish Saxena (Georgia Tech); Aamer Jaleel (NVIDIA); Moinuddin Qureshi (Georgia Tech),
    to appear at Micro 2024, November  2024