Damien Hardy

Damien Hardy

Assistant Professor, University of Rennes I


Contact information

IRISA, ALF Research Group
Postal address: IRISA Campus universitaire de Beaulieu 35042 Rennes Cedex FRANCE
E-mail address: Damien.Hardy@irisa.fr
Room: E-319
Telephone: +33 2 99 84 75 73


Research

My current research interests include hardware reliability, and real-time systems, mainly estimation of the worst-case execution time (WCET) of applications.

Activities

Current PhD students

  • Viet Anh Nguyen (since january 2015): WCET for many core architectures. Co-supervized by Isabelle Puaut (50%).

Current projects

  • Capacites: Parallel computations for safety critical real-time applications (2014 – 2018)
  • SECODE: Secure Codes to thwart Cyber-physical Attacks (2016 – 2018)
  • ARGO: WCET-Aware Parallelization of Model-Based Applications for Heterogeneous Parallel Systems

Software

  • Heptane is an open-source static WCET estimation tool
  • COST-ET is an estimation and exploration tool to provide qualitative trends of datacenter design choices on the total cost of ownership

Teaching

  • Operating systems – master degree of computer science
  • Real-time systems – BSc degree Embedded automotive systems

Publications

Academic Journals

Static Probabilistic Worst Case Execution Time Estimation for Architectures with Faulty Instruction Caches. D. Hardy, I. Puaut. Journal of Real-Time Systems 2015.
Optimizing Data-Center TCO with Scale-Out Processors. B. Grot, D. Hardy, P. Lotfi-Kamran, B. Falsafi, C. Nicopoulos, Y. Sazeides. IEEE Micro, Special Issue on Energy-Aware Computing. Volume 32, issue 5. Sep/Oct 2012.
WCET analysis of instruction cache hierarchies. D. Hardy, I. Puaut. Journal of Systems Architecture, volume 57, issue 7, pages 677-694, August 2011.

International Conferences

Cache-Persistence-Aware Response-Time Analysis for fixed-priority preemptive systems. S. A. Rashid, G. Nelissen, D. Hardy, B. Akesson, I. Puaut, E. Tovar. In Proc. of the 28th Euromicro Conference on Real-Time Systems, Toulouse, France, July 2016. to appear.

Probabilistic WCET estimation in presence of hardware for mitigating the impact of permanent faults. D. Hardy, I. Puaut, Y. Sazeides. Design, Automation and Test in Europe. Dresden, Germany, March 2016. (Best paper award).
Speeding up Static Probabilistic Timing Analysis. S. Milutinovic, J. Abella, D. Hardy, E. Quiñones, I. Puaut, F. Cazorla. 28th GI/ITG International Conference on Architecture of Computing Systems. Porto, Portugal,March 2015.
On the Comparison of Deterministic and Probabilistic WCET Estimation Techniques. J. Abella, D. Hardy, I. Puaut, E. Quiñones, F. Cazorla. In Proc. of the 26th Euromicro Conference on Real-Time Systems, Madrid, Spain, July 2014.
Static probabilistic Worst Case Execution Time Estimation for architectures with Faulty Instruction Caches. D. Hardy, I. Puaut. In the 21st International Conference on Real-Time Networks and Systems (RTNS), Sophia Antipolis, France, October 2013. (Best paper award).
An Analytical Framework for Estimating TCO and Exploring Data Center Design Space. D. Hardy, M. Kleanthous, I. Sideris, A. Saidi, E. Ozer and Y. Sazeides. In Proc. of the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS-2013), Apr. 2013.
The Performance Vulnerability of Architectural and Non-architectural Arrays to Permanent Faults. D. Hardy, I. Sideris, N. Ladas, Y. Sazeides. In Proc. of the 45th Annual IEEE/ACM International Symposium on Microarchitecture, Vancouver, Canada, December 2012.
Thermal characterization of cloud workloads on a power-efficient server-on-chip. D. Milojevic, S. Idgunji, D. Jevdjic, E. Özer, P. Lotfi-Kamran, A. Panteli, A. Prodromou, C. Nicopoulos, D. Hardy, B. Falsafi, Y. Sazeides. In Proc. of the 30th IEEE International Conference on Computer Design, Montreal, Canada, October 2012.
Scalable Fixed-Point Free Instruction Cache Analysis. D. Hardy, B. Lesage, I. Puaut. In Proc. of the 32nd IEEE Real-Time Systems Symposium, Vienna, Austria, December 2011.
Shared Data Cache Conflicts Reduction for WCET Computation in Multi-Core Architectures. B. Lesage, D. Hardy, I. Puaut. In Proc. of the 18th Real-Time and Network Systems, Toulouse, France, November 2010. PDF
Using Bypass to Tighten WCET Estimates for Multi-Core Processors with Shared Instruction Caches. D. Hardy, T. Piquet, I. Puaut. In Proc. of the 30th IEEE Real-Time Systems Symposium, Washington D.C., USA, December 2009. PDF
Estimation of Cache Related Migration Delays for Multi-Core Processors with Shared Instruction Caches. D. Hardy, I. Puaut. In Proc. of the 17th Real-Time and Network Systems, Paris, France, October 2009. PDF
WCET analysis of multi-level non-inclusive set-associative instruction caches. D. Hardy, I. Puaut. In Proc. of the 29th IEEE Real-Time Systems Symposium, Barcelona, Spain, December 2008. PDF
Predictable code and data paging for real-time systems. D. Hardy, I. Puaut. In Proc. of the 20th Euromicro Conference on Real-Time Systems, Prague, Czech Republic, July 2008. PDF
Predictable paging in real-time systems: a compiler approach. I. Puaut, D. Hardy. In Proc. of the 19th Euromicro Conference on Real-Time Systems, Pisa, Italy, July 2007. PDF

Workshop/Research Report

Scheduling of parallel applications on many-core architectures with caches: bridging the gap between WCET analysis and schedulability analysis. Viet Ahn Nguyen, Damien Hardy, Isabelle Puaut. 9th Junior Workshop on Real Time computing, in conjunction with RTNS 2015, Lille, France, November 2015

EETCO: A tool to Estimate and Explore the Implications of Datacenter Design Choices on the TCO and the Environmental Impact. D. Hardy, I. Sideris, A. Saidi and Y. Sazeides. Workshop on Energy-efficient Computing for a Sustainable World in conjunction with the 44th Annual IEEE/ACM International Symposium on Microarchitecture (Micro-44) , Port Alegre, Brazil, Dec. 2011.

WCET analysis of multi-level set-associative data caches. B. Lesage, D. Hardy, I. Puaut. 9th Int’l Workshop on Worst-Case Execution Time Analisis (WCET 2009), Dublin, Ireland, July 2009. PDF

Using Bypass to Tighten WCET Estimates for Multi-Core Processors with Shared Instruction Caches. D. Hardy, T. Piquet, I. Puaut. Research Report IRISA, No 6907, April 2009. PDF

Impact of instruction cache replacement policy on the tightness of WCET estimation. A. Junier, D. Hardy, I. Puaut. 2nd Junior Researcher Workshop on Real-Time Computing (JRWRTC 2008), Rennes, France, Oct 2008. PDF

WCET analysis of multi-level set-associative instruction caches. D. Hardy, I. Puaut. Research Report IRISA, No 6574, June 2008. PDF

Predictable paging in real-time systems: an ILP formulation. D. Hardy, I. Puaut. Ecole d’été Temps Réel (ETR’07), Nantes, France, Sep 2007. PDF

Thesis

Analyse pire cas pour processeurs multi-coeurs disposant de caches partagés. Damien Hardy PhD Thesis Université de Rennes I, December 2010.PDF

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