Vlad Rusu (team leader, http://researchr.org/profile/vladrusu): I was a PhD student in Computer Science from 1993 to 1996 at the university of Nantes, where I worked on using hybrid automata and temporal logic for verifying real-time systems. After my PhD I was a research and teaching assistant at the University of Nantes for one year and then a post-doc for 18 months at SRI International (formerly, Stanford Research Institute, Silicon Valley, California) in the group developing and using the PVS proof assistant. I joined Inria in 1999 as a permanent researcher, at Inria Rennes (199-2008) and at Inria Lille from 2008 on. I was a first a member in the DaRT team, then the team leader its last year of existence (2012) under that name. The team was reborn in 2013, with a new composition, project, and name. My research interests are formal methods in a broad sense, for specifying, testing, and verifying systems.
Jean-Luc Dekeyser http:/www.lifl.fr/~dekeyser received his PhD degree in computer science from the university of Lille in 1986. He was a fellow at CERN Geneva. After a few years at the Supercomputing Computation Research Institute in Florida State University, where he worked on high performance computing for Monté-Carlo methods in High Energy Physics, he joined in 1988 the University of Lille as an assistant professor. There he worked on the data-parallel paradigm and vector processing. He created a research group working on High Performance Computing in the CNRS lab in Lille. He is currently Professor in computer science at University of Lille. He has headed the DaRT Inria project during 8 years. His research interests include embedded systems, System on Chip co-design, synthesis and simulation, performance evaluation, high performance computing, model driven engineering, dynamic reconfiguration, and 3D-chips.
Frédéric Guyomarch http://www.lifl.fr/~guyomarc received his PhD in Computer Science in 2000 and got a position as associate professor at the University of Rennes, where his research interests focused on high-performances computing, from the algorithms for numerical computation to their implementation for sequential or parallel execution. Then, in 2007, he moved to the University of Lille where he continues working on numerical algorithms to solve electromagnetic problems and also on compilation techniques to generate optimized code for such algorithms. He is currently involved in the formal design of programming languages for HoMade-based architectures.
Samy Meftali http://www.lifl.fr/~meftali received his PhD degree in computer science from the University of Grenoble 1 in 2001. After that he has been associate professor at the University of Lille 1, where he got his HDR (Habilitation à Diriger des Recherches) in 2010. He leaded several national and international research projects as ANR Famous, Euromed 3+3 and AUF. He worked on memory architectures, heterogeneous simulation environment, MDE for SoC design and SystemC modelling, before moving in the last few years to dynamically reconfigurable systems design with a focus on the control aspect and hardware supports for dynamic and partial reconfiguration.
Philippe Marquet http://www.lifl.fr/~marquet/ is an associate professor in computer science at the University of Lille 1. He obtained his PhD from the University of Lille 1 as well. He has been a co-founder of the Inria Dart team, the predecessor of Dreampal, and before that, he was a member of the West team of LIFL. Within the Gaspard2 project of DaRT he was mostly involved in the MppSoC (massively parallel processing on a SoC) and H-noc (a network on chip for synchronous communication and asynchronous computation) subprojects. His research interests include systems and networks on chip, data-parallel computation, and dynamically reconfigurable systems. Philippe Marquet is Vice President of the SIF, the French Informatics Society. He is also in charge of the Master of Computer Science at the University of Lille 1.
Rabie Ben Atitallah http://www.lifl.fr/~benatita/ is an associate professor in computer science at the University of Valenciennes and member of the LAMIH laboratory within the DIM (Decision, Interaction, and Mobility) team. He is also an external collaborator of the Dreampal team. He is an IEEE member and a member of High Performance and Embedded Architecture and Compilation (HiPEAC) European Network of Excellence. He received his PhD in Computer Science from the University of Lille1 in March 2008. Between March 2008 and August 2009, he had a post-doctoral position at INRIA Lille-Nord Europe and the University of Valenciennes. His research interests include Embedded system design, MultiProcessor System-on-Chip (MPSoC), low power-aware design, virtual prototyping, simulation, and dynamic reconfigurable computing.
- Andrei ARUSOAIE
- Ahmad Chadi ALJENDI
- Hana KRICHENE
The (Synchronous Communication & Asynchronous Computation) SCAC project aims at the design and implementation of a new massively parallel execution model to facilitate the development of high-performance embedded solutions without being affected by the increasing complexity of these applications. This model is characterized by Synchronous Communication achieved by a grid of a huge number of Slave Control Unit ( The SCUs) and Asynchronous Computation achieved by clusters of processors. Each cluster is controlled by its local SCU which is potentially connected to its neighbors via a regular network. All the system is controlled by a Master Controller Unit (the MCU).
- Karim Mohamed ALI
- Venkatasubramanian VISWANATHAN
- Wissem CHOUCHENE
Advanced 3D FPGA Technology for Dynamic Reconfigurable Massively Parallel Architectures
we propose in the frame of this project a design environment for an advanced 3D FPGA taking into account the following steps:
At the technological level, we propose the definition and the implementation of a parallel reconfiguration model that takes profit from the innovative 3D technology to allow fast and simultaneous programming of several logic fabric regions.
At the architectural level, we focus on the definition and the implementation of an efficient execution model dedicated for massively parallel and dynamic reconfigurable architectures mapped on 3D FPGA.
At the application level, we propose the validation of the previous contributions through video processing application using first a multi FPGA board and 3D technology when available.