Research Projects

LOTR (Lord Of The RISCs)

  • Type: ANR PRC, Oct 2023 – Sept 2027
  • Partners: TARAN, PACAP, CEA-List
  • Objective: Lord Of The RISCs (LOTR) is a novel flow for designing highly customized RISC-V processor microarchitectures for embedded and IoT platforms. The LOTR flow operates on a description of the processor Instruction Set Architecture (ISA). It can automatically infer synthesizable Register Transfer Level (RTL) descriptions of a large number of microarchitecture variants with different performance/cost trade-offs. In addition, the flow integrates two domain-specific toolboxes dedicated to the support of timing predictability (for safety-critical systems) and security (through hardware protection mechanisms).
  • Key TARAN Investigators: S. Derrien, S. Rokicki
  • Website: TBA

RADYAL (Resource-Aware DYnamically Adaptable machine Learning)

  • Type: ANR PRC, Oct 2023 – Apr 2027
  • Partners: LIRIS / INSA Lyon, Inria (TARAN, Ctrl-A), GIPSA-lab / UGA
  • Objective: Nowadays, for many applications, the performance requirements of a DNN model deployed on a given hardware platform are not static but evolving dynamically as its operating conditions and environment change. RADYAL studies original interdisciplinary approaches that allow DNN models to be dynamically configurable at run-time on a given reconfigurable hardware accelerator architecture, depending on the external environment, following an approach based on feedback loops and control theory.
  • Key TARAN Investigators: M. Traiola, O. Sentieys
  • Website: TBA

Re-Trusting (REliable hardware for TRUSTworthy artificial INtelliGence)

  • Type: ANR PRCE, Jan. 2022 – Sep. 2025.
  • Partners: INL, LIP6, TARAN, THALES.
  • Objective: The RE-TRUSTING project develops fault models and performs failure analysis of HW-AIs to study their vulnerability with the goal of “explaining” HW-AI. Explaining HW-AI means ensuring that the hardware is error-free and that the AI hardware does not compromise the AI prediction accuracy and does not bias AI decision-making. In this regard, the project aims at providing confidence and trust in decision-making based on AI by explaining the hardware wherein AI algorithms are being executed.
  • Key TARAN Investigators: A. Kritikakou, O. Sentieys, S. Filip, M. Traiola, F. Fernandes dos Santos,
  • Website:

FASY (FAult-aware timing behaviour for safety-critical multicore SYstems)

  • Type: ANR young researcher, Feb. 2022 – Dec. 2025.
  • Partners: TARAN (PI:A. Kritikakou).
  • Objective: FASY will answering the two-fold challenge of time-predictable and reliable multicore systems through functional and timing analysis of applications behaviour, fault-aware WCET estimation and design of cores with time-predictable execution, under faults.
  • Key Investigators: A. Kritikakou, M. Traiola, O. Sentieys.
  • Website:

LeanAI (Dynamic Precision Training on the Edge)

  • Type: Labex CominLabs, Oct. 2021 – Sep. 2024.
  • Objective: LeanAI will attack the problem of training deep neural networks on edge devices at the arithmetic and algorithmic levels and explore the design of new mixed numerical precision hardware architectures that are at the same time more energy-efficient and offer increased performance in a resource-restricted environment. The expected outcome of the project includes new mixed-precision algorithms for neural network training, together with open-source tools for hardware and software training acceleration at the arithmetic level on edge devices.
  • Key TARAN Investigators: S. Filip, O. Sentieys, S. Derrien.

Sniffer (Non-intrusive monitoring of mains operated equipment)

  • Type: Feb. 2020 – Dec. 2022.
  • Partners: TARAN, DGA/MI.
  • Objective: Based on the SmartSense platform and on high-frequency traces of the power consumption of individ- ual electrical appliances and building-level power monitoring, the aim of Sniffer is the detection and surveillance of equipment connected to the mains supply.
  • Key TARAN Investigators: O. Sentieys.

SHNoC (Scalable Hybrid Network-on-Chip)

  • Type: ANR young researcher, Feb. 2019 – Jan. 2022.
  • Partners: TARAN (PI: C. Killian).
  • Objective: Study the process compatibility of ONoC, WiNoC and Electrical NoC, to define a topology of an architecture hybridizing these three technologies, and to demonstrate that this architecture is more efficient with respect to traffic characteristics between cores and quality of service targeted.
  • Key Investigators: C. Killian.

AdequateDL (Approximating Deep Learning Accelerators)

  • Type: ANR PRC, Jan. 2019 – Dec. 2022.
  • Partners: TARAN, INL, LIRMM, CEA-LIST.
  • Objective: Explore how approximations can improve performance and energy efficiency of hardware accelerators in deep-learning inference and training. Outcomes include a framework for accuracy exploration and the demonstration of performance and energy-efficiency gains of the proposed adequate accelerators with regards to conventional CPU/GPU computing platforms.
  • Key TARAN Investigators: S. Filip, O. Sentieys.

Rakes (Radio Killed an Electronic Star)

  • Type: ANR PRC, Jun. 2019 – Jun. 2023.
  • Partners: TIMA, TARAN, Lab-STICC.
  • Objective: Speed-up parallel programming with broadcast communications based on hybrid wireless/wired network on chip. We intend to study how on-chip mixed wired/wireless Network on Chip can solve the scalability of coherent shared memory in multi/many-core architectures. We plan to study several alternatives and to provide (a) a virtual platform for evaluation and (b) an actual implementation of the solutions.
  • Key TARAN Investigators: D. Chillet, C. Killian, O. Sentieys.

Opticall2 (on-chip OPTIcal interconnect for ALL to ALL communications)

  • Type: ANR PRCE, Dec. 2018 – Nov. 2022.
  • Partners: INL, TARAN, C2N, CEA-LETI, Kalray.
  • Objective: Design broadcast- enabled optical communication links in manycore architectures at wavelengths around 1.3μm. We aim to fabricate an optical broadcast link for which the optical power is equally shared by all the destinations and to propose and design a new broadcast-aware cache coherence protocol allowing hundreds of computing clusters and memories to be interconnected.
  • Key TARAN Investigators: D. Chillet, C. Killian, O. Sentieys.

Flodam (Software Flow to Harden Multicore Architectures)

  • Type: DGA RAPID, Oct. 2017 – Nov. 2021.
  • Partners: Temento, TARAN, Onera. FLODAM is an industrial research project for methodologies and tools dedi- cated to the hardening of embedded multicore processors.
  • Objective: (i) Evaluate the impact of environments on resistance to faults, (ii) explore architecture solutions for improving fault tolerance of multicores, and (iii) test and evaluate the proposed fault tolerant architecture solutions and compare the results under different scenarios (space, avionics).
  • Key TARAN Investigators: A. Kritikakou, O. Sentieys, S. Rokicki.

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