JPDC’14
Title: Adaptive Thread Mapping Strategies for Transactional Memory Applications
Authors: M. Castro (UFRGS), L. Goes (PUC Minas), J-F. Méhaut (UJF/NANOSIM)
Journal of Parallel and Distributed Computing (JPDC), Volume 74, Number 9, pp 2845-2859, September 2014
Jean-François MEHAUT
Jean-François Méhaut is Professor of Computer Science at the
Université Joseph Fourier (UJF) since 2003. He is a member of
the LIG and head of the Nanosi team. His current research
includes embedded systems as well as all aspects of high performance computing including runtime systems,
multithreading and memory management in NUMA
multiprocessors, multi-core and hybrid programming.
Jean-François supervised 26 PhD student.
He has spent one year at the Argonne National Laboratory
of Department of Energy (DOE, Illinois, USA). He is currently involved
in the EU FP7 ICT Mont-Blanc projects. He is a member of the joint
laboratory for petascale computing (JLPC) between INRIA and University of Illinois at Urbana Champaign (UIUC), Argonne National Laboratory (ANL/MCS) and the BSC (Barcelona). He is also PI of the
FP7 IRSES HPC GA (High Performance Computing for Geophysics Applications).
