Dmitry Burlyaev

Looks like me

Now

Me: 2nd year PhD student @ INRIA (2012-2015);

Research: Specification and Synthesis of Fault-Tolerant Circuits.

Aims: formal methods development for automatic circuit synthesis/transformation in order to introduce fault-tolerance properties with minimum hardware/speed/power overheads;

Supervision: Alain Girault and Pascal Fradet.

Short Bio

2010-2012: MSc in Embedded Systems, TU Delft (cum laude) .

Thesis @ Innovative Solutions In Space B.V.:

            “System-level Fault-Tolerance Analysis of Small Satellite On-board Computers

2006-2010: BEng in Automation and Control, Bauman Moscow State Technical University(cum laude).

Thesis @ JSC “Russian Space Systems”.

Contact Info

Tel.: (+33) 78 – 24 – 24 – one-six-nine

Email: my_name.my_surname@inria.fr