PhD defense of Rabab Bouziane (PACAP Team), December 7, 2018 – 14:00, in Metivier meeting room

You are cordially invited to attend the PhD defense of Rabab Bouziane (PACAP Team) that will be held Friday, December 7, 2018 at 14:00, in Metivier meeting room and for a drink in Sein meeting room.

Jury members :
Christine Rochange, Professor, Université de Toulouse
Kévin Marquet, Associate Professor, Insa Lyon
Abdoulaye Gamatié, Senior Researcher, CNRS/LIRMM
Pierre Boulet, Professor, Université de Lille
Sandrine Blazy, Professor, Université de Rennes 1
Erven Rohou, Senior Researcher, Inria

Title : Software-level Analysis and Optimization to Mitigate the Cost of Write Operations on Non-Volatile Memories

Abstract :
Traditional memories such as SRAM, DRAM and Flash have faced during the last years, critical challenges related to what modern computing systems required: high performance, high storage density and low power. As the number of CMOS transistors is increasing, the leakage power consumption becomes a critical issue for energy-efficient systems. SRAM and DRAM consume too much energy and have low density and Flash memories have a limited write endurance. Therefore, these technologies can no longer ensure the needs in both embedded and high-performance computing domains. The future memory systems must respect the energy and performance requirements. Since Non Volatile Memories (NVMs) appeared, many studies have shown prominent features where such technologies can be a potential replacement of the conventional memories used on-chip and off-chip. NVMs have important qualities in storage density, scalability, leakage power, access performance and write endurance. Nevertheless, there are still some critical drawbacks of these new technologies. The main drawback is the cost of write operations in terms of latency and energy consumption. We propose a compiler-level optimization that reduces the number of write operations by elimination the execution of redundant stores, called silent stores. A store is silent if it’s writing in a memory address the same value that is already stored at this address. The LLVM-based optimization elimates the identified silent stores in a program by not executing them. Furthermore, the cost of a write operation is highly dependent on the used NVM and its non-volatility called retention time; when the retention time is high then the latency and the energetic cost of a write operation are considerably high and vice versa. Based on that, we propose an approach applicable in a multi- bank NVM where each bank is designed with a specific retention time. We analysis a program and we compute the worst-case lifetime of a store instruction to allocate data to the most appropriate NVM bank.

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