When Thursday Dec 10th from 9:15 for a virtual coffee. If you wish to join the virtual coffee, please send an email to Liliana dot cucu at inria dot fr
The visio presentation starts from 9:30.
Titre: Tracking timing anomalies
Bio: Mathieu Jan obtained his engineer diploma in 2003 and got a PhD in 2006 on the subject of management of data on grid architectures in an INRIA laboratory. He joined the “Commissariat à l’Energie Atomique” (the French DoE) in 2007. His main research interests are around real-time and embedded systems (network on chip, scheduling, mapping, low-power, formal modeling and verification). He is senior expert on these subjects at CEA since 2014 and he obtained an Habilitation à Diriger des Recherche (HDR) in 2016 from the Paris-Sud University. He participated in a technology transfer of a methodology to design and execute safety-critical real-time systems targeting automotive and energy distribution fields, now made availabe by Krono-Safe. He is member of the various program committees, such as the International Real-Time and Network Systems (RTNS) conference, wrote 7 patents, has co-advised 5 PhD thesis and is the director of 3 on-going PhD thesis. He spent the whole year 2019 as visiting scholar at the University of California, Berkeley (UCB) in the group of Prof. Edward Lee.
Abstract: Computer architectures used in safety-critical domains are subjected to worst-case execution time analysis. The presence of performance-driven microarchitectures may trigger undesired timing phenomena, called timing anomalies, and complicate the timing analysis. In this talk, we introduce two types of such undesired timing phenomena, called counter-intuitive and amplifications timing anomalies at the pipeline level. We then present our approach to detect these different types of timing anomalies within programs running over various pipelines, in particular the designed abstract formal hardware models as well as the verification strategy based on model-checking.
