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Duco van Amstel

Duco's Identity photo

Who am I ?

Hi, my name is Duco and I am one of the PhD students on the Corse team. I joined the team from the start as I already was a member of the same group of people working on compilers. My PhD started in april 2013 but before that I graduated from the Ecole Normale Supérieure de Lyon with a research-focused MSc. in Computer Science (I did this at the same time as François Gindraud my fellow team member and PhD student). The experience and skills that I acquired during courses and internships cover a wide variety of subjects:

  • simulation of physical systems and their control (automatics)
  • distributed computing and the associated scheduling issues
  • network and flow-control algorithms
  • cryptography
  • optimization and compiling

I finally decided on compilation as my PhD subject after an industry internship at Kalray during which I worked on the implementation and optimization of cryptographic standards. This is also the reason why my PhD is based on a combined industry-academic research project. My working time is split in two between my research at Inria on the Corse team and my work as an engineer at Kalray.

What kind of research am I doing ?

@Corse

My academic research focuses on tiling optimizations for data-flow languages on many-core architectures. The goal is to exploit the information provided by the data-flow graph of a program to reduce as much as possible the amount of memory communications between:

  1. the cache of a single core and the shared memory
  2. the seperate cores
  3. the different pieces of memory as memory tends to get scathered among groups of cores when their number grows

To achieve this I want to influence the assignement of data-flow agents (the equivalent of imperative programming functions) to cores and/or groups of cores. Depending on the size of the code of these agents and the amount and forms of data-structures that they manipulate it may be advantageous to assign two agents to the same group or to two seperate ones. Besides this research I also perform as the system administrator for the GCG team.

@Kalray

My position as a member of the compiler team at Kalray is closely associated with the research work that I perform at Inria. My main occupations are the development and maintainance of the Linear Assembler Optimizer tool that is used additionnaly to their customized version of the GCC compiler. This tool is the perfect industrial-grade testbed for the optimizations that are being developed by the Corse team. Additionally I also assist Kalray on their Network-on-Chip infrastructure that link the cores of their chip by providing theoretical insight and background into flow-management and Quality-of-Service (QoS) issues.

Duco paraglidingWhere to find me when I’m not working ?

My free time is divided between multiple activities among which the most important are reading, listening to music, paragliding and enjoying life in general. My personal website contains some of my research done during my internships and my own projects but also my travel-log of a 6 month sabbatical in New Zealand before starting my PhD.

Publications

Publications HAL de Duco van Amstel

2016

Conference papers

titre
Generalized cache tiling for dataflow programs
auteur
Łukasz Domagała, Duco Van Amstel, Fabrice Rastello
article
Conference on Languages, Compilers, Tools, and Theory for Embedded Systems, Jun 2016, Santa Barbara, United States. pp.10, 2016, Proceedings of the 17th ACM SIGPLAN/SIGBED Conference on Languages, Compilers, Tools, and Theory for Embedded Systems. 〈10.1145/2907950.2907960〉
Accès au bibtex
BibTex

Theses

titre
Data Locality on Manycore Architectures
auteur
Duco Van Amstel
article
Distributed, Parallel, and Cluster Computing [cs.DC]. Université Grenoble-Alpes, 2016. English
Accès au texte intégral et bibtex
https://hal.inria.fr/tel-01358312/file/manuscript.pdf BibTex
titre
Optimisation de la localité des données sur architectures manycœurs
auteur
Duco Van Amstel
article
Architectures Matérielles [cs.AR]. Université Grenoble Alpes, 2016. Français. 〈NNT : 2016GREAM019〉
Accès au texte intégral et bibtex
https://tel.archives-ouvertes.fr/tel-01508540/file/VANAMSTEL_2016_archivage.pdf BibTex

2014

Conference papers

titre
Guaranteed Services of the NoC of a Manycore Processor
auteur
Benoît Dupont de Dinechin, Durand Yves, Duco Van Amstel, Alexandre Ghiti
article
International Workshop on Network-on-Chips, Dec 2014, Cambridge, United Kingdom. pp.6, Proceedings of the International Workshop on Network-on-Chips 2014
Accès au bibtex
BibTex
titre
Time-critical computing on a single-chip massively parallel processor
auteur
Benoît Dupont de Dinechin, Duco Van Amstel, Marc Poulhies, Guillaume Lager
article
European Design and Automation Association. Conference on Design, Automation & Test in Europe, Mar 2014, Dresden, Germany. pp.97:1-97:6, 2014, Proceedings of the Conference on Design, Automation & Test in Europe 2014. 〈http://www.date-conference.com/front〉
Accès au bibtex
BibTex

Reports

titre
A Tiling Perspective for Register Optimization
auteur
Fabrice Rastello, Sadayappan Ponnuswany, Duco Van Amstel
article
[Research Report] RR-8541, Inria. 2014, pp.24
Accès au texte intégral et bibtex
https://hal.inria.fr/hal-00998915/file/RR-8541-Inria.pdf BibTex